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LTC4555EUD#TRPBF

P1-P3P4-P6P7-P8
LTC4555
4
4555fc
For more information www.linear.com/LTC4555
Typical perForMance characTerisTics
V
CC
Short-Circuit Current I
BAT
vs V
BAT
pin FuncTions
TEMPERATURE (°C)
–40
SHORT-CIRCUIT CURRENT (mA)
170
150
130
110
90
70
50
20 60
4555 G01
–20 0
40 80 100
T
A
= –40°C
V
BAT
(V)
2.5
I
BAT
(µA)
22
20
18
16
14
12
10
4.0 5.0
4555 G02
3.0 3.5
4.5 5.5 6.0
V
CC
= 1.8V
V
CC
= 3V
T
A
= 25°C
T
A
= 85°C
T
A
= 85°C
T
A
= 25°C
T
A
= –40°C
SHDN (Pin 1): Controller Driven Shutdown Pin. This pin
should be high (DV
CC
) for normal operation and low to
activate a low current shutdown mode.
V
SEL
(Pin 2): V
CC
Voltage Select Pin. A low level selects V
CC
= 1.8V while driving this pin to DV
CC
selects V
CC
= 3V.
DV
CC
(Pin 3): Supply Voltage for the Controller Side I/O
Pins (C
IN
, R
IN
, DATA). When below 1.1V, the V
CC
supply
is disabled. This pin should be bypassed with a 0.1µF
ceramic capacitor close to the pin.
NC (Pins 4, 6, 12, 16): No Connect.
V
BAT
(Pin 5): V
CC
Supply Input. This pin can be between
3V and 6V for normal operation. V
BAT
quiescent current
reduces to <1µA in shutdown. This pin should be bypassed
with a 0.1µF ceramic capacitor close to the pin.
V
CC
(Pin 7): SIM Card V
CC
Supply. A 1µF low ESR capacitor
needs to be connected close to the V
CC
pin for stable opera-
tion. This pin is discharged to GND during shutdown.
I/O (Pin 8): SIM-Side Data I/O. The SIM card output must
be on an open-drain driver capable of sour
cing >1mA.
RST (Pin 9): Reset Output Pin for the SIM Card.
GND (Pin 10): Ground for the SIM and Controller. Proper
grounding and bypassing is required to meet 14kV ESD
specifications.
CLK (Pin 11): Clock Output Pin for the SIM Card. This
pin is pulled to ground during shutdown. Fast rising and
falling edges necessitate careful board layout for the CLK
node.
C
IN
(Pin 13): Clock Input from the Controller.
R
IN
(Pin 14): Reset Input from the Controller.
DATA (Pin 15): Controller Side Data I/O. This pin is used
for bidirectional data transfer. The controller output must
be an open-drain configuration. The open-drain output
must be capable of sinking greater than 1mA.
Exposed Pad (Pin 17): GND. Must be soldered to PCB.
LTC4555
5
4555fc
For more information www.linear.com/LTC4555
block DiagraM
applicaTions inForMaTion
The LTC4555 provides both regulated power and internal
level translators to allow low voltage controllers to interface
with 1.8V or 3V SIMs or smart cards. The part meets all
ETSI, IMT-2000 and ISO7816 requirements for SIM and
smart card interfaces.
V
CC
Voltage Regulator
The V
CC
voltage regulator is a 50mA low dropout (LDO)
regulator with a digitally selected 1.8V or 3V output.
The output voltage is selected via the V
SEL
pin. The output
is internally current limited and is capable of surviving an
indefinite short to GND.
The V
CC
output should be bypassed with a 1µF capacitor.
The LTC4555 can use either a low ESR ceramic capacitor
or a tantalum electrolytic capacitor on the V
CC
pin, with
no special ESR requirements.
V
BAT
should be bypassed with a 0.1µF ceramic capacitor.
Level Translators
All SIMs and smart cards contain a clock input, a reset
input and a bidirectional data input/output. The LTC4555
provides level translators to allow controllers to com
-
municate with the SIM. The CLK and RST lines to the
SIM are
level shifted from the controller supply (GND to
DV
CC
) to the SIM supply (GND to V
CC
). The data input to
the SIM requires an open-drain output on the controller.
On-chip pull-up resistors are provided for both the DATA
and I/O lines.
Shutdown Modes
The LTC4555 enters a low current shutdown mode by pull
-
ing the SHDN pin low. The SHDN pin is an active low input
that the controller can use to directly shut down the part.
ESD Protection
All pins that connect to the SIM/smart card will withstand
14kV of human body model ESD. In order to ensure prop
-
er ESD protection, careful board layout is required. The
GND pin should be tied directly to a GND plane. The V
CC
capacitor should be located very close to the V
CC
pin and
tied directly to the GND plane.
V
BAT
(3V TO 6V)
CELL PHONE
PROCESSOR
INTERFACE
SIM/
SMART CARD
INTERFACE
SHDN
V
SEL
R
IN
C
IN
DATA
RST
CLK
I/0
DV
CC
V
BAT
C1
1µF
GND
50mA LDO
C3
0.1µF
C2
0.1µF
LTC4555
PROCESSOR
V
CC
SHUTDOWN
PIN
V
SIM
VOLTAGE
SELECT
RESET
FROM
PROCESSOR
CLOCK
FROM
PROCESSOR
DATA TO/
FROM SIM
1.8V/3V
AT 50mA
RESET
CLOCK
BIDIRECTIONAL
I/O
4555 BD
20k 10k
1
2
14
13
15
10
8
11
9
7
53
V
CC
LTC4555
6
4555fc
For more information www.linear.com/LTC4555
3.00 ±0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45 ±0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.45 ± 0.10
(4-SIDES)
0.75 ±0.05
R = 0.115
TYP
0.25 ±0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
15 16
2
0.50 BSC
0.200 REF
2.10 ±0.05
3.50 ±0.05
0.70 ±0.05
0.00 – 0.05
(UD16) QFN 0904
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691 Rev Ø)
package DescripTion
Please refer to http://www.linear.com/product/LTC4555#packaging for the most recent package drawings.
P1-P3P4-P6P7-P8

LTC4555EUD#TRPBF

Mfr. #:
Buy LTC4555EUD#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators SIM Pwr S & Level Translator
Lifecycle:
New from this manufacturer.
Delivery:
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