ISL9000IRKPZ

7
FN9217.4
March 11, 2008
FIGURE 14. TURN ON/TURN OFF RESPONSE FIGURE 15. LINE TRANSIENT RESPONSE (3.3V OUTPUT)
FIGURE 16. LINE TRANSIENT RESPONSE (2.8V OUTPUT) FIGURE 17. LOAD TRANSIENT RESPONSE
FIGURE 18. PSRR vs FREQUENCY FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
Typical Performance Curves (Continued)
1
3
0
2
0
100 200 300 400 500 600 700 8000
TIME (µs)
VO1 (V)VEN (V)
5
V
O1
= 3.3V
V
IN
= 5.0V
I
L
1 = 300mA
C
L
1, C
L
2 = 1µF
C
BYP
= 0.01µF
900 1000
VO2 (10mV/DIV)
I
L
2 = 300mA
V
O2
= 2.8V
400µs/DIV
V
O
= 3.3V
I
LOAD
= 300mA
3.6V
4.3V
10mV/DIV
C
LOAD
= 1µF
C
BYP
= 0.01µF
400µs/DIV
V
O
= 2.8V
I
LOAD
= 300mA
3.5V
4.2V
10mV/DIV
C
LOAD
= 1µF
C
BYP
= 0.01µF
100µs/DIV
V
O
(25mV/DIV)
I
LOAD
300mA
100µA
V
IN
= 2.8V
V
O
= 1.8V
0.1k 1k 10k 100k 1M
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
PSRR (dB)
V
IN
= 3.6V
V
O
= 1.8V
I
O
= 10mA
C
BYP
= 0.1µF
C
LOAD
= 1µF
SPECTRAL NOISE DENSITY (nV/Hz)
1000
100
10
1
0.1
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
V
IN
= 3.6V
V
O
= 1.8V
I
LOAD
= 10mA
C
BYP
= 0.1µF
C
IN
= 1µF
C
LOAD
= 1µF
ISL9000
8
FN9217.4
March 11, 2008
Pin Description
Typical Application
PIN
NUMBER
PIN
NAME TYPE DESCRIPTION
1 VIN Analog I/O Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
2 EN1 Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3 EN2 Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4 CBYP Analog I/O Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR2
output release after LDO-2
output reaches 94% of its specified voltage level. (200ms delay per 0.01µF).
6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane.
7POR1
Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low):
Internally connected to VO1 through 100kΩ resistor.
8POR2
Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low):
Internally connected to VO2 through 100kΩ resistor.
9VO2
Analog I/O LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10 VO1 Analog I/O LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
C1, C4, C5: 1µF X5R ceramic capacitor
C2: 0.1µF X7R ceramic capacitor
ISL9000
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
10
9
8
7
6
1
2
3
4
5
VIN (2.3 TO 6.5V)
ENABLE1
ENABLE2
VOUT 1
VOUT 2
RESET 1
RESET 2
C1 C2 C3 C4 C5
C3: 0.01µF X7R ceramic capacitor
OFF
ON
OFF
ON
(200ms delay,
C3 = 0.01µF)
(2ms delay)
VOUT 2 TOO LOW
VOUT 2 OK
VOUT 1 TOO LOW
VOUT 1 OK
ISL9000
9
FN9217.4
March 11, 2008
Block Diagram
Functional Description
The ISL9000 contains two high performance LDOs. High
performance is achieved through a circuit that delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9000 adjusts its biasing to achieve the
lowest standby current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9000 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power-up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDOs power-up in their specified
sequence.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge.
VO2
LDO
ERROR
AMPLIFIER
IS1 1VQEN1
LDO-1
LDO-2
POR
COMPARATOR
VOK1
POR1
VREF
TRIM
VIN
VO1
VO2
POR2
POR1
GND
EN2
EN1
CONTROL
LOGIC
POR2
DELAY
POR1
DELAY
VOLTAGE
REFERENCE
GENERATOR
BANDGAP AND
TEMPERATURE
SENSOR
UVLO
VOK2
VOK1
1.00V
0.94V
0.90V
IS1
IS2
QEN1
QEN2
VO1
VO2
100k100k
CPOR
CBYP
VO1
~1.0V
VOK2
POR2
ISL9000

ISL9000IRKPZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators W/ANNEAL LW NOISE HI PSRRLD 10LD 3X3 2 85
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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