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A1148ELHLT

P1-P3P4-P6P7-P9P10-P12
Low Current Ultrasensitive Two-Wire
Chopper-Stabilized Unipolar Hall Effect Switches
A1147 and
A1148
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall element. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of the output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulation-
demodulation process. The undesired offset signal is separated
from the magnetic field-induced signal in the frequency domain,
through modulation. The subsequent demodulation acts as a
modulation process for the offset, causing the magnetic field-
induced signal to recover its original spectrum at baseband, while
the DC offset becomes a high-frequency signal. The magnetic-
sourced signal then can pass through a low-pass filter, while
the modulated DC offset is suppressed. This configuration is
illustrated in figure 2.
The chopper stabilization technique uses a 200 kHz high
frequency clock. For demodulation process, a sample and hold
technique is used, where the sampling is performed at twice the
chopper frequency (400 kHz). This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
and faster signal-processing capability. This approach desensi-
tizes the chip to the effects of thermal and mechanical stresses,
and produces devices that have extremely stable quiescent Hall
output voltages and precise recoverability after temperature
cycling. This technique is made possible through the use of a
BiCMOS process, which allows the use of low-offset, low-noise
amplifiers in combination with high-density logic integration
and sample-and-hold circuits.
The repeatability of magnetic field-induced switching is affected
slightly by a chopper technique. However, the Allegro high-
frequency chopping approach minimizes the affect of jitter and
makes it imperceptible in most applications. Applications that
are more likely to be sensitive to such degradation are those
requiring precise sensing of alternating magnetic fields; for
example, speed sensing of ring-magnet targets. For such applica-
tions, Allegro recommends its digital device families with lower
sensitivity to jitter. For more information on those devices,
contact your Allegro sales representative.
Figure 2. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)
Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
Low Current Ultrasensitive Two-Wire
Chopper-Stabilized Unipolar Hall Effect Switches
A1147 and
A1148
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
For additional general application information, visit the Allegro
Web site at www. allegromicro.com.
GND
A114x
VCC
V+
0.01 μF
A
B
B
GND
ECU
Package UA Only
A
B
Maximum separation 5 mm
R
SENSE
C
BYP
Figure 3. Typical application circuit
Typical Application Circuit
The A114x family of devices must be protected by an external
bypass capacitor, C
BYP
, connected between the supply, VCC,
and the ground, GND, of the device. C
BYP
reduces both external
noise and the noise generated by the chopper-stabilization func-
tion. As shown in figure 3, a 0.01 μF capacitor is typical.
Installation of C
BYP
must ensure that the traces that connect it to
the A114x pins are no greater than 5 mm in length.
All high-frequency interferences conducted along the supply
lines are passed directly to the load through C
BYP
, and it serves
only to protect the A114x internal circuitry. As a result, the load
ECU (electronic control unit) must have sufficient protection,
other than C
BYP
, installed in parallel with the A114x.
A series resistor on the supply side, RS (not shown), in combina-
tion with C
BYP
, creates a filter for EMI pulses.
When determining the minimum V
CC
requirement of the A114x
device, the voltage drops across R
S
and the ECU sense resistor,
R
SENSE
, must be taken into consideration. The typical value for
R
SENSE
is approximately 100 Ω.
Low Current Ultrasensitive Two-Wire
Chopper-Stabilized Unipolar Hall Effect Switches
A1147 and
A1148
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
The device must be operated below the maximum junction
temperature of the device, T
J(max)
. Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating T
J
. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
JA
, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
JC
, is
relatively small component of R
JA
. Ambient air temperature,
T
A
, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
P
D
= V
IN
×
I
IN
(1)
T = P
D
×
R
JA
(2)
T
J
= T
A
+ ΔT (3)
For example, given common conditions such as: T
A
= 25°C,
V
CC
= 12 V, I
CC
= 4 mA, and R
JA
= 140 °C/W, then:
P
D
= V
CC
×
I
CC
= 12 V
×
4 mA = 48 mW
T = P
D
×
R
JA
= 48 mW
×
140 °C/W = 7°C
T
J
= T
A
+ T = 25°C + 7°C = 32°C
A worst-case estimate, P
D(max)
, represents the maximum allow-
able power level (V
CC(max)
, I
CC(max)
), without exceeding T
J(max)
,
at a selected R
JA
and T
A
.
Example: Reliability for V
CC
at T
A
=
150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
R
JA
=
165°C/W, T
J(max)
=
165°C, V
CC(max)
=
24 V, and
I
CC(max)
=
17
mA.
Calculate the maximum allowable power level, P
D(max)
. First,
invert equation 3:
T
max
= T
J(max)
– T
A
= 165
°C
–
150
°C = 15
°C
This provides the allowable increase to T
J
resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= T
max
÷ R
JA
= 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
÷ I
CC(max)
= 91 mW ÷ 17 mA = 5 V
The result indicates that, at T
A
, the application and device can
dissipate adequate amounts of heat at voltages ≤V
CC(est)
.
Compare V
CC(est)
to V
CC(max)
. If V
CC(est)
≤ V
CC(max)
, then reli-
able operation between V
CC(est)
and V
CC(max)
requires enhanced
R
JA
. If V
CC(est)
≥ V
CC(max)
, then operation between V
CC(est)
and
V
CC(max)
is reliable under these conditions.
P1-P3P4-P6P7-P9P10-P12

A1148ELHLT

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