LTC4067
9
4067f
CLPROG (Pin 1): Current Limit Program Pin. Connect-
ing a 1% resistor, R
CLPROG
, to ground programs input
current limit depending on the selected operating mode.
Operating mode and input current limit are programmed
depending on the I
LIM0
and I
LIM1
pin voltages according
to the following table:
Table 1. I
LIM
Programming
I
LIM0
I
LIM1
I
LIMIT
(A) MODE
L H 0 SUSPEND
L L 200V/R
CLPROG
Low Power
H H 1000V/R
CLPROG
High Power
HL 2 CLDIS
The maximum CLPROG resistance value should be no more
than 5k. Ground to disable the current limit function.
⎯
C
⎯
H
⎯
R
⎯
G (Pin 2): Open Drain Charge/Fault Status Output.
When the battery is being charged, the
⎯
C
⎯
H
⎯
R
⎯
G pin is pulled
low by an internal N-channel MOSFET. When the timer runs
out or the charge current drops below a programmable
level or the supply is removed, the
⎯
C
⎯
H
⎯
R
⎯
G pin is forced
into a high impedance state. Float or tie to ground when
not in use.
NTC (Pin 3): Thermistor sense input to the thermistor moni-
toring circuits. Under normal operation, tie a thermistor
from the NTC pin to ground and a resistor of equal value
from the NTC pin to IN. Connect the NTC pin to ground
to disable this feature.
I
LIM0
(Pin 4): Current Limit Control Input. Float or connect
to ground when not in use (see Table 1).
I
LIM1
(Pin 5): Current Limit Control Input. Float or connect
to ground when not in use (see Table 1).
OVI (Pin 6): Overvoltage Protection Sense Input. Connect
to ground when not in use. Bypass to OVP with a 10nF
capacitor.
OVP (Pin 7): Overvoltage Protection Output. Drive output
for an external high-voltage protection PFET. Float when
not in use.
PROG (Pin 8): Charge Current Program Pin. Connecting
a 1% resistor, R
PROG
, to ground programs the charge
current during the constant-current portion of the charge
cycle according to the following formula:
I
CC-CHG
(A) = 1000V/R
PROG
If the PROG pin is pulled above the V
SD
threshold or left
fl oating, the LTC4067 enters low power SHUTDOWN
mode to conserve power, in this way an open-drain driver
in series with the PROG resistor serves as an ENABLE
control. Grounding this pin disables charge current limit
and turns off
⎯
C
⎯
H
⎯
R
⎯
G status signal.
GATE (Pin 9): External Ideal Diode Gate Connection. This
pin controls the gate of an optional external P-channel
MOSFET transistor used to supplement the internal ideal
diode. The source of the P-channel MOSFET should be
connected to OUT and the drain should be connected to
BAT. It is important to maintain high impedance on this
pin and minimize all leakage paths.
BAT (Pin 10): Single-Cell Li-Ion Battery. Depending on
available power and load, a Li-Ion battery on BAT will either
deliver system power to OUT through the ideal diode or
be charged from the battery charger.
OUT (Pin 11): Output Voltage of the PowerPath™ Controller
and Input Voltage of the Battery Charger. The majority of
the portable product should be powered from OUT. The
LTC4067 will partition the available power between the
external load on OUT and the internal battery charger.
Priority is given to the external load and any extra power is
used to charge the battery. An ideal diode from BAT to OUT
ensures that OUT is powered even if the load exceeds the
allotted input current from IN or if the IN power source is
removed. OUT should be bypassed with a low impedance
multilayer ceramic capacitor of at least 10μF.
IN (Pin 12): USB Input Voltage. IN will usually be connected
to the USB port of a computer or a DC output wall adapter.
IN should be bypassed with a low impedance multilayer
ceramic capacitor of at least 1μF.
Exposed Pad (Pin 13): Ground. The exposed pad is
ground and must be soldered to the PC board for proper
functionality and for maximum heat transfer.
PI FU CTIO S
UUU
PowerPath is a trademark of Linear Technology Corporation.
