MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (MAX5259)
(V
REF
= +2.5V, GND = 0, C
DOUT
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= +3V and
T
A
= +25°C.)
V
DD
Rise-to-CS Fall-Setup Time t
VDCS
5 µs
LDAC Pulse Width Low t
LDAC
40 20 ns
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
t
CLL
40 ns
CS Pulse Width High t
CSW
90 ns
SCLK Clock Frequency (Note 5)
SCLK Pulse Width High t
CH
40 ns
SCLK Pulse Width Low t
CL
40 ns
CS Fall-to-SCLK Rise-Setup Time
SCLK Rise-to-CS Rise-Hold Time
DIN to SCLK Rise-to-Setup Time
t
DS
40 ns
DIN to SCLK Rise-to-Hold Time t
DH
0ns
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
t
DO1
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
t
DO2
210
ns
CS Rise-to-SCLK Rise-Setup
Time
t
CS1
40 ns
Note 1: INL and DNL are measured with R
L
referenced to ground. Nonlinearity is measured from the first code that is greater than or
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of V
OUT
.
Note 3: Guaranteed by design, not production tested.
Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for t
LDAC
or longer after CS goes high.
Note 5: When DOUT is not used. If DOUT is used, f
CLK
(max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
