AD688
Rev. B | Page 6 of 16
THEORY OF OPERATION
The AD688 consists of a buried Zener diode reference,
amplifiers and associated thin-film resistors as shown in
Figure 3. The temperature compensation circuitry provides the
device with a temperature coefficient of 1.5 ppm/°C or less.
Amplifier A1 performs several functions. A1 primarily acts to
amplify the Zener voltage to the required 20 V. In addition, A1
also provides for external adjustment of the 20 V output
through Pin 5 (GAIN ADJ). Using the bias compensation
resistor between the Zener output and the noninverting input to
A1, a capacitor can be added at the noise reduction pin (Pin 7)
to form a low-pass filter and reduce the noise contribution of
the Zener to the circuit. Two matched 12 kΩ nominal thin-film
resistors (R4 and R5) divide the 20 V output in half.
Ground sensing for the circuit is provided by amplifier A2. The
noninverting input (Pin 9) senses the system ground and forces
the midpoint of resistors R4 and R5 to be a virtual ground.
Pin 12 (BAL ADJ) can be used for fine adjustment of this
midpoint transfer.
Amplifiers A3 and A4 are internally compensated and are used
to buffer the voltages at Pin 6 and Pin 8 as well as to provide a
full Kelvin output. Thus, the AD688 has a full Kelvin capability
by providing the means to sense a system ground, and forced
and sensed outputs referenced to that ground.
R3
R
B
R1
R2
R4
R5
R6
GAIN
ADJ
GND
SENSE
+IN
NC
V
LOW
BAL
ADJ
NC
A4 IN
–V
S
+V
S
–10V OUT
FORCE
–10V OUT
SENSE
+10V OUT
FORCE
+10V OUT
SENSEA3 IN
V
HIGH
NOISE
REDUCTION
A1
A4
A3
A2
AD688
7 6 4 3
1
14
2
15
16
5 9 10 8 12 11 13
00815-003
NC = NO CONNECT
Figure 3. Functional Block Diagram
AD688
Rev. B | Page 7 of 16
APPLICATIONS
The AD688 can be configured to provide ±10 V reference
outputs as shown in Figure 4. The architecture of the AD688
provides ground sense and uncommitted output buffer
amplifiers which offer the user a great deal of functional
flexibility. The AD688 is specified and tested in the
configuration shown in Figure 4. The user may choose to take
advantage of other configuration options available with the
AD688; however performance in these configurations is not
guaranteed to meet the stringent data sheet specifications.
Unbuffered outputs are available at Pin 6 and Pin 8. Loading of
these unbuffered outputs will impair circuit performance.
Amplifiers A3 and A4 can be used interchangeably. However,
the AD688 is tested (and the specifications are guaranteed) with
the amplifiers connected as indicated in Figure 4. When either
A3 or A4 is unused, its output force and sense pins should be
connected and the input tied to ground.
Two outputs of the same voltage polarity may be obtained by
connecting both A3 and A4 to the appropriate unbuffered
output on Pin 6 or Pin 8. Performance in these dual output
configurations will typically meet data sheet specifications.
R3
R
B
R1
R2
R4
R5
R6
A1
A4
AD688
A3
A2
SYSTEM
GROUND
+10V
+15V SUPPLY
–10V
–15V SUPPLY
SYSTEM
GROUND
0.1
µ
F
0.1
µ
F
7
6
4
3
1
14
2
15
16
5 9
10
8
12
11
13
00815-004
Figure 4. +10 V and −10 V Outputs
CALIBRATION
Generally, the AD688 will meet the requirements of a precision
system without additional adjustment. Initial output voltage
error of 2 mV and output noise specs of 6 µV p-p allow for
accuracies of 12 to 16 bits. However, in applications where an
even greater level of accuracy is required, additional calibration
may be called for. The provision for trimming has been made
through the use of the GAIN ADJ and BAL ADJ pins (Pin 5 and
Pin 12, respectively).
The AD688 provides a precision 20 V span with a center tap
which is used with the buffer and ground sense amplifiers to
achieve the ±10 V output configuration. GAIN ADJ and
BAL ADJ can be used to trim the magnitude of the 20 V span
voltage and the position of the center tap within the span. The
gain adjustment should be performed first. Although the trims
are not interactive within the device, the gain trim will move the
balance trim point as it changes the magnitude of the span.
Figure 5 shows the gain and balance trims of the AD688. A
100 kΩ 20-turn potentiometer is used for each trim. The
potentiometer for the gain trim is connected between Pin 6
(V
HIGH
) and Pin 8 (V
LOW
) with the wiper connected to Pin 5
(GAIN ADJ). The potentiometer is adjusted to produce exactly
20 V between Pin 1 and Pin 15, the amplifier outputs. The
balance potentiometer, also connected between Pin 6 and Pin 8
with the wiper to Pin 12 (BAL ADJ), is then adjusted to center
the span from +10 V to −10 V.
Input impedance on both the GAIN ADJ and the BAL ADJ pins
is approximately 150 kΩ. The gain adjustment trim network
effectively attenuates the 20 V across the trim potentiometer by
a factor of about 1150 to provide a trim range of –5.8 mV to
+12.0 mV with a resolution of approximately 900 µV/turn
(20-turn potentiometer). The balance adjustment trim network
attenuates the trim voltage by a factor of about 1250, providing
a trim range of ±8 mV with a resolution of 800 µV/turn.
Trimming the AD688 introduces no additional errors over
temperature, so precision potentiometers are not required.
When balance adjustment is not necessary, Pin 12 should be left
floating. If gain adjustment is not required, Pin 5 should also be
left floating.
R3
R
B
R1
R2
R4
R5
R6
A1
A4
AD688
A3
A2
SYSTEM
GROUND
+10V
+15V SUPPLY
–10V
–15V SUPPLY
SYSTEM
GROUND
0.1
µ
F
0.1
µ
F
100k
20T
BALANCE
ADJUST
100k
20T
GAIN ADJUST
+15V
NOISE
REDUCTION
1µF
7
6
4
3
1
14
2
15
16
5
9
10
8
12 11
13
20k
00815-005
Figure 5. Gain and Balance Adjustment with Noise Reduction
AD688
Rev. B | Page 8 of 16
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD688 is typically less than
6 µV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz
bandwidth is approximately 840 µV p-p. The dominant source
of this noise is the buried Zener which contributes
approximately 140 nV/√Hz. In comparison, the op amps
contribution is negligible. Figure 6 shows the 0.1 Hz to 10 Hz
noise of a typical AD688.
00815-006
1µV
1mV
5s
100
90
10
0%
Figure 6. 0.1 Hz to 10 Hz Noise
If further noise reduction is desired, an optional capacitor can
be added between the noise reduction pin and ground as shown
in Figure 5. This will form a low-pass filter with the 5 kΩ R
B
on
the output of the Zener cell. A 1 µF capacitor will have a 3 dB
point at 32 Hz and will reduce the high frequency noise (to
1 MHz) to about 250 µV p-p. Figure 7 shows the 1 MHz noise of
a typical AD688 both with and without a 1 µF capacitor.
200µV
50µs
C
N
= 1µF
NO C
N
00815-007
Figure 7. Effect of 1 µF Noise Reduction Capacitor on Broadband Noise
TURN ON TIME
Upon application of power (cold start), the time required for
the output voltage to reach its final value within a specified
error is the turn on settling time. Two components normally
associated with this are: time for active circuits to settle and
time for thermal gradients on the chip to stabilize. Figure 8 and
Figure 9 show the turn on characteristics of the AD688. They
show the settling time to be about 600 µs. Note the absence of
any thermal tails when the horizontal scale is expanded to
2 ms/cm in Figure 9.
00815-008
100
90
10
0%
+V
S
–V
S
+V
OUT
10V
1mV
100µs
10V
Figure 8. Turn On Characteristics: Electrical Turn On
00815-009
100
90
10
0%
+V
S
–V
S
+V
OUT
10V
1mV
2ms
10V
Figure 9. Turn On Characteristics: Extended Time Scale
Output turn on time is modified when an external noise
reduction capacitor is used. When present, this capacitor
presents an additional load to the internal Zener diodes current
source, resulting in a somewhat longer turn on time. In the case
of a 1 µF capacitor, the initial turn on time is approximately
100 ms (Figure 10).
When the noise reduction feature is used, a 20 kΩ resistor
between Pin 6 and Pin 2 is required for proper startup.
00815-010
100
90
10
0%
+V
S
–V
S
+V
OUT
10V
1mV
20ms
10V
Figure 10. Turn On With 1 µF C
N

AD688AQ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Voltage References High perf +/-10V Ref IC
Lifecycle:
New from this manufacturer.
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