PCK940L_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 4 April 2006 9 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
9.1 Timing diagrams
Fig 3. Propagation delay (t
PD
) test reference Fig 4. LVCMOS_CLK propagation delay (t
PD
) test
reference
The time from the PLL controlled edge to the
non-controlled edge, divided by the time between
PLL controlled edges, expressed as a percentage.
The pin-to-pin skew is defined as the worst-case
difference in propagation delay between any two
similar delay paths within a single device.
Fig 5. Output duty cycle Fig 6. Output-to-output skew
(1) output 2.4 V; input 2.0 V (V
CC
= 3.3 V)
output 1.8 V; input 1.7 V (V
CC
= 2.5 V)
(2) output 0.55 V; input 0.8 V (V
CC
= 3.3 V)
output 0.6 V; input 0.7 V (V
CC
= 2.5 V)
Fig 7. Transition time test reference
002aab893
t
PD
PECL_CLK
Qn
V
ICR
V
CC
0.5V
CC
GND
PECL_CLK
V
i(p-p)
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t
PD
LVCMOS_CLK
Qn
V
CC
0.5V
CC
GND
V
CC
0.5V
CC
GND
002aab291
t
p
V
CC
0.5V
CC
GND
T
o
δ
o
= (t
p
÷ T
o
× 100 %)
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t
sk(o)
V
CC
0.5V
CC
GND
V
CC
0.5V
CC
GND
002aab292
t
f
(1)
(2)
t
r