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PCK940LBD,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
PCK940L_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 4 April 2006 4 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
6. Functional description
Refer to Figure 1 “Functional diagram of PCK940L”.
6.1 Function table
7. Limiting values
8. Static characteristics
Table 3. Function table
LVCMOS_CLKSEL Input
0 PECL_CLK
1 LVCMOS_CLK
Table 4. Power supply voltage
Supply pin Voltage level
V
CC2
2.5 V or 3.3 V ± 5%
V
CC1
2.5 V or 3.3 V ± 5%
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.3 +3.6 V
V
I
input voltage −0.3 V
DD
+ 0.3 V
I
I
input current - ±20 mA
T
stg
storage temperature −40 +125 °C
Table 6. Static characteristics (3.3 V V
CC
, 3.3 V outputs)
T
amb
=0
°
Cto70
°
C; V
CC2
= 3.3 V
±
5 %; V
CC1
= 3.3 V
±
5%
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage LVCMOS_CLK 2.4 - V
CC2
V
V
IL
LOW-level input voltage LVCMOS_CLK - - 0.8 V
V
i(p-p)
peak-to-peak input voltage PECL_CLK 500 - 1000 mV
V
ICR
common mode input voltage range PECL_CLK V
CC
− 1.4 - V
CC
− 0.6 V
V
OH
HIGH-level output voltage I
OH
= −20 mA 2.4 - - V
V
OL
LOW-level output voltage I
OH
= 20 mA - - 0.5 V
I
I
input current - - ±200 µA
C
i
input capacitance - 4.0 - pF
C
PD
power dissipation capacitance per output - 10 - pF
Z
o
output impedance 18 23 28 Ω
I
CC(max)
maximum supply current - 0.5 1.0 mA
PCK940L_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 4 April 2006 5 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
Table 7. Static characteristics (3.3 V V
CC
, 2.5 V outputs)
T
amb
=0
°
Cto70
°
C; V
CC2
= 3.3 V
±
5 %; V
CC1
= 2.5 V
±
5%
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage LVCMOS_CLK 2.4 - V
CC2
V
V
IL
LOW-level input voltage LVCMOS_CLK - - 0.8 V
V
i(p-p)
peak-to-peak input voltage PECL_CLK 500 - 1000 mV
V
ICR
common mode input voltage range PECL_CLK V
CC
− 1.4 - V
CC
− 0.6 V
V
OH
HIGH-level output voltage I
OH
= −20 mA 1.8 - - V
V
OL
LOW-level output voltage I
OH
= 20 mA - - 0.5 V
I
I
input current - - ±200 µA
C
i
input capacitance - 4.0 - pF
C
PD
power dissipation capacitance per output - 10 - pF
Z
o
output impedance - 23 - Ω
I
CC(max)
maximum supply current - 0.5 1.0 mA
Table 8. Static characteristics (2.5 V V
CC
, 2.5 V output)
T
amb
=0
°
Cto70
°
C; V
CC2
= 2.5 V
±
5 %; V
CC1
= 2.5 V
±
5%
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage LVCMOS_CLK 2.0 - V
CC2
V
V
IL
LOW-level input voltage LVCMOS_CLK - - 0.8 V
V
i(p-p)
peak-to-peak input voltage PECL_CLK 500 - 1000 mV
V
ICR
common mode input voltage range PECL_CLK V
CC
− 1.0 - V
CC
− 0.6 V
V
OH
HIGH-level output voltage I
OH
= −20 mA 1.8 - - V
V
OL
LOW-level output voltage I
OH
= 20 mA - - 0.5 V
I
I
input current - - ±200 µA
C
i
input capacitance - 4.0 - pF
C
PD
power dissipation capacitance per output - 10 - pF
Z
o
output impedance 18 23 28 Ω
I
CC(max)
maximum supply current - 0.5 1.0 mA
PCK940L_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 4 April 2006 6 of 16
Philips Semiconductors
PCK940L
Low voltage 1 : 18 clock distribution chip
9. Dynamic characteristics
[1] Tested using standard input levels, production tested at 150 MHz.
[2] Across temperature and voltage ranges, includes output skew.
[3] For a specific temperature and voltage, includes output skew.
Table 9. Dynamic characteristics (3.3 V V
CC
, 3.3 V output)
T
amb
=0
°
Cto70
°
C; V
CC2
= 3.3 V
±
5 %; V
CC1
= 3.3 V
±
5%
Symbol Parameter Conditions Min Typ Max Unit
f
oper(max)
maximum operating frequency - - 250 MHz
t
PLH
LOW-to-HIGH propagation
delay
PECL_CLK ≤ 150 MHz
[1]
2.0 2.7 3.8 ns
LVCMOS_CLK ≤ 150 MHz
[1]
1.8 2.5 3.0 ns
PECL_CLK > 150 MHz 2.0 2.9 3.7 ns
LVCMOS_CLK > 150 MHz 1.8 2.4 3.2 ns
t
sk(o)
output skew time output-to-output
PECL_CLK
[1]
- - 200 ps
LVCMOS_CLK
[1]
- - 150 ps
t
sk(pr)
process skew time part-to-part
PECL_CLK < 150 MHz
[1][2]
- - 1.4 ns
LVCMOS_CLK < 150 MHz
[1][2]
- - 1.2 ns
PECL_CLK > 150 MHz
[1][2]
- - 1.7 ns
LVCMOS_CLK > 150 MHz
[1][2]
- - 1.4 ns
PECL_CLK
[1][3]
- - 850 ps
LVCMOS_CLK
[1][3]
- - 750 ps
δ
o
output duty cycle LCVMOS_CLK; input δ =50%
f
clk
< 134 MHz 45 50 55 %
f
clk
≤ 250 MHz 40 50 60 %
PECL_CLK; input δ =50%
f
clk
< 134 MHz 35 50 65 %
f
clk
≤ 250 MHz 40 50 60 %
t
r
rise time output; from 0.5 V to 2.4 V 0.3 - 1.1 ns
t
f
fall time output; from 2.4 V to 0.5 V 0.3 - 1.1 ns
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PCK940LBD,151

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Buy PCK940LBD,151
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 1:18 250MHZ 32LQFP
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