6.42
IDT709089/79S/L
High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
15
3242 drw 19
IDT709089/79
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
15
/A
14
(1)
CE
1
CE
0
V
CC
V
CC
IDT709089/79
IDT709089/79
IDT709089/79
Control Inputs
Control Inputs
Control Inputs
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/W
OE
,
Functional Description
The IDT709089/79 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT709089/79's for
depth expansion configurations. When the Pipelined output mode is
enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-
activate the outputs.
Depth and Width Expansion
The IDT709089/79 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the various chip
enables in order to expand two devices in depth.
The IDT709089/79 can also be used in applications requiring ex-
panded width, as indicated in Figure 4. Since the banks are allocated at
the discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 16-bit or
wider applications.
Figure 4. Depth and Width Expansion with IDT709089/79
NOTE:
1. A15 is for IDT709089, A14 is for IDT709079.
