CENTELLAX • Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
DC Bias
The UATM30M2C is biased by apply-
ing a positive voltage to the drain
(Vdd), then setting the drain current
(Idd) using a negative voltage on the
gate (Vg1).
When zero volts is applied to the gate,
the drain to source channel is open;
this results in high Idd. When Vg1 is
biased negatively, the channel is
pinched off and Idd decreases.
The nominal bias is Vdd=5.0V,
Idd=150mA. Improved noise or power
performance can be achieved with
application-specific biasing.
Gain Control
Dynamic gain control is available
when operating the amplifier in
the linear gain region. Negative
voltage applied to the second
gate (Vg2) reduces amplifier gain.
RF Power Detection
RF output power can be calcu-
lated from the difference between
the RF detector voltage and the
DC detector voltage, minus a DC
offset. Please consult the power
detector application note avail-
able from the Centellax webpage.
Low-Frequency Use
The UATM30M2C has been
designed so that the bandwidth
can be extended to low frequen-
cies. The low end corner fre-
quency of the device is primarily
determined by the external bias-
ing and AC coupling circuitry.
Matching
The amplifier incorporates on-
chip termination resistors on the
RF input and output. These resis-
tors are RF grounded through on-
chip capacitors, which are small
and become open circuits at fre-
quencies below 1GHz.
A pair of gate and drain termina-
tion bypass pads are provided for
connecting external capacitors
required for the low frequency
extension network. These capac-
itors should be 10x the value of
the DC blocking capacitors.
DC Blocks
The amplifier is DC coupled to the
RF input and output pads; DC
voltage on these pads must be
isolated from external circuitry.
For operation above 2GHz, a
series DC-blocking capacitor with
minimum value of 20pF is recom-
mended; operation above 40MHz
requires a minimum of 120pF.
Inductor Bias
DC bias applied to the drain (Vdd)
must be decoupled with an off-
chip RF choke inductor. The
amount of bias inductance will
determine the low frequency
operating point. Inductive biasing
can also be applied to the chip
through the RF output.
For many applications above
2GHz, a bondwire from the Vdd
pad will suffice as the biasing
inductor. Ensure the correct bond
length as shown in the assembly
diagrams.
Supplemental Specifications
Parameter Description Min Typ Max
Vdd Drain Bias Voltage 3V 5V 8V
Idd Drain Bias Current — 150mA 250mA
Vg1 1st Gate Bias Voltage -4V — 0V
Vg2 2nd Gate Bias Voltage Vdd-Vg2<7V N/C +4V
P
in
Input Power (CW) 20dBm
P
dc
Power Dissipation 0.75W
T
ch
Channel Temperature 150°C
Θ
ch
Thermal Resistance (T
case
=85°C) 18°C/W
