AD7781CRUZ Datasheet AD7781BRUZ, AD7781CRZ, AD7781BRZ-REEL | P4-P6

AD7781

Rev. 0 | Page 3 of 16

SPECIFICATIONS

= 2.7 V to 5.25 V, V

REF

= AV

, DV

= 2.7 V to 5.25 V, GND = 0 V, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

ADC CHANNEL

Output Update Rate (f

ADC

) 10 Hz FILTER = 1, settling time = 3/f

ADC

16.7 Hz FILTER = 0, settling time = 2/f

ADC

No Missing Codes

20 Bits

Resolution, Peak-to-Peak See Table 7 and Table 8

RMS Noise See Table 7 and Table 8

Integral Nonlinearity ±6 ppm FSR

Offset Error ±6 µV Gain = 128 with FILTER = 1

±200 µV Gain = 1 with FILTER = 1

±1 µV Gain = 128 with FILTER = 0

±10 µV Gain = 1 with FILTER = 0

Offset Error Drift vs. Temperature ±10 nV/°C Gain = 128

±150 nV/°C Gain = 1 with FILTER = 1

±10 nV/°C Gain = 1 with FILTER = 0

Full-Scale Error ±0.25 % of FS

Gain Drift vs. Temperature ±2 ppm/°C

Power Supply Rejection 100 dB Gain = 128, FILTER = 1, AIN = 7.81 mV

120 dB Gain = 128, FILTER = 0, AIN = 7.81 mV

Normal Mode Rejection

50 Hz, 60 Hz 63 75 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, f

ADC

= 16.7 Hz

72 90 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, f

ADC

= 10 Hz

Common-Mode Rejection

DC 90 dB Gain = 1, AIN = 1 V

90 dB Gain = 128, AIN = 7.81 mV

50 Hz, 60 Hz 110 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

ANALOG INPUTS

Differential Input Voltage Range ±V

REF

/gain V

REF

= REFIN(+) − REFIN(−),

gain = 1 or 128

Absolute AIN Voltage Limits

GND + 100 mV AV

− 100 mV V Gain = 1

GND + 450 mV AV

− 1.1 V Gain = 128, FILTER = 0

GND + 1.1 AV

− 1.1 V Gain = 128, FILTER = 1, AV

≤ 3.6 V

GND + 1.5 AV

− 1.5 V Gain = 128, FILTER = 1, AV

> 3.6 V

Average Input Current ±1 nA Gain = 1

±250 pA Gain = 128

Average Input Current Drift ±3 pA/°C

REFERENCE

External REFIN Voltage AV

V REFIN = REFIN(+) − REFIN(−)

Reference Voltage Range

0.5 AV

Absolute REFIN Voltage Limits

GND − 30 mV AV

+ 30 mV V

Average Reference Input Current 400 nA/V

Average Reference Input Current

Drift

±0.15 nA/V/°C

Normal Mode Rejection Same as for analog inputs

Common-Mode Rejection 110 dB

BRIDGE POWER-DOWN SWITCH

(BPDSW)

Controlled via the PDRST

9 Ω

Allowable Current

30 mA Continuous current

AD7781

Rev. 0 | Page 4 of 16

Parameter Min Typ Max Unit Test Conditions/Comments

INTERNAL CLOCK

Frequency 64 − 3% 64 + 3% kHz

Duty Cycle 50:50 %

LOGIC INPUTS

SCLK, FILTER, GAIN, PDRST

Input Low Voltage, V

INL

0.4 V DV

= 3 V

0.8 V DV

= 5 V

Input High Voltage, V

INH

1.8 V DV

= 3 V

2.4 V DV

= 5 V

SCLK (Schmitt-Triggered Input)

Hysteresis

100 mV DV

= 3 V

140 mV DV

= 5 V

Input Currents ±2 µA V

= DV

or GND

Input Capacitance 10 pF All digital inputs

LOGIC OUTPUT (DOUT/RDY)

Output High Voltage, V

− 0.6 V DV

= 3 V, I

SOURCE

= 100 µA

4 V DV

= 5 V, I

SOURCE

= 200 µA

Output Low Voltage, V

0.4 V DV

= 3 V, I

SINK

= 100 µA

0.4 V DV

= 5 V, I

SINK

= 1.6 mA

Floating-State Leakage Current ±2 µA

Floating-State Output Capacitance 10 pF

Data Output Coding Offset binary

POWER REQUIREMENTS

Power Supply Voltage

to GND 2.7 5.25 V

Power Supply Currents

Current

Gain = 1 115 µA AV

= 3 V

130 160 µA AV

= 5 V

Gain = 128 (B Grade) 300 µA AV

= 3 V

350 400 µA AV

= 5 V

Gain = 128 (C Grade) 330 µA AV

= 3 V

420 500 µA AV

= 5 V

(Power-Down/Reset Mode) 10 µA

Temperature range is −40°C to +105°C.

This specification is not production tested but is supported by characterization data at initial product release.

Digital inputs are equal to DV

or GND.

AD7781

Rev. 0 | Page 5 of 16

TIMING CHARACTERISTICS

= 2.7 V to 5.25 V, DV

= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV

, unless otherwise noted.

Table 3.

Parameter

Limit at T

MIN

, T

MAX

Unit Test Conditions/Comments

Read

100 ns min SCLK high pulse width

100 ns min SCLK low pulse width

0 ns min SCLK active edge to data valid delay

60 ns max DV

= 4.75 V to 5.25 V

80 ns max DV

= 2.7 V to 3.6 V

10 ns min

SCLK inactive edge to DOUT/RDY

high

130 ns max

Reset

100 ns min

PDRST

low pulse width

FILTER/GAIN change to data valid delay

120 ms typ Update rate = 16.7 Hz

300 ms typ Update rate = 10 Hz

Sample tested during initial release to ensure compliance. All input signals are specified with t

= t

= 5 ns (10% to 90% of DV

) and timed from a voltage level of 1.6 V.

See Figure 3.

The values of t

are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the V

or V

limits.

SCLK active edge is falling edge of SCLK.

The

PDRST

high to data valid delay is typically 1 ms longer than t

because the internal oscillator requires time to power up and settle.

Circuit and Timing Diagrams

SINK

(1.6mA WITH DV

= 5V,

100µA WITH DV

= 3V)

SOURCE

(200µA WITH DV

= 5V,

100µA WITH DV

= 3V)

1.6V

OUTPUT

50pF

PDRST

(INPUT)

DOUT/RDY

(OUTPUT)

08162-004

GAIN OR FILTER

(INPUT)

08162-002

Figure 2. Load Circuit for Timing Characterization

DOUT/RDY

(OUTPUT)

MSB LSB

SCLK

(INPUT)

08162-003

Figure 3. Read Cycle Timing Diagram

Figure 4. Resetting the AD7781

DOUT/RDY

(OUTPUT)

08162-005

Figure 5. Changing Gain or Filter Option

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7781CRUZ

Mfr. #:

Buy AD7781CRUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 20-Bit Pin-Prog Ultra low Power

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AD7781CRUZ

AD7781CRUZ

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