© 2000 Fairchild Semiconductor Corporation DS006213 www.fairchildsemi.com
September 1986
Revised February 2000
DM74ALS245A Octal 3-STATE Bus Transceiver
DM74ALS245A
Octal 3-STATE Bus Transceiver
General Description
This advanced low power Schottky device contains 8 pairs
of 3-STATE logic elements configured as octal bus trans-
ceivers. These circuits are designed for use in memory,
microprocessor systems and in asynchronous bidirectional
data buses. Two way communication between buses is
controlled by the (DIR) input. Data transmits either from the
A bus to the B bus or from the B bus to the A bus. Both the
driver and receiver outputs can be disabled via the (G
)
enable input which causes outputs to enter the high imped-
ance mode so that the buses are effectively isolated.
Features
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Non-inverting logic output
■ Glitch free bus during power up and down
■ 3-STATE outputs independently controlled on A and B
buses
■ Low output impedance to drive terminated transmission
lines to 133Ω
■ Switching response specified into 500Ω/50 pF
■ Specified to interface with CMOS at V
OH
= V
CC
− 2V
■ PNP inputs to reduce input loading
■ Switching specifications guaranteed over full tempera-
ture and V
CC
range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either HIGH or LOW Logic Level
Order Number Package Number Package Description
DM74ALS245AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS245ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS245AMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS245AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Control
Inputs Operation
G
DIR
L L B Data to A Bus
L H A Data to B Bus
H X Hi-Z