PCA9549_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 13 July 2009 13 of 25
NXP Semiconductors
PCA9549
Octal bus switch with individually I
2
C-bus controlled enables
10. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 6 Ω typical R
on
and the 50 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] C
b
= total capacitance of one bus line in pF.
Table 8. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
t
PD
propagation delay A to B;
V
DD
= 4.5 V to 5.5 V
- 0.25
[1]
- 0.25
[1]
ns
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - µs
t
HD;STA
hold time (repeated) START condition
[2]
4.0 - 0.6 - µs
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - µs
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - µs
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - µs
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - µs
t
HD;DAT
data hold time 0
[3]
3.45 0
[3]
0.9 µs
t
SU;DAT
data set-up time 250 - 100 - ns
t
r
rise time of both SDA and SCL
signals
- 1000 20 + 0.1C
b
[4]
300 ns
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[4]
300 ns
C
b
capacitive load for each bus line - 400 - 400 pF
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
t
VD;DAT
data valid time HIGH-to-LOW - 1 - 1 µs
LOW-to-HIGH - 0.6 - 0.6 µs
t
VD;ACK
data valid acknowledge time - 1 - 1 µs
RESET
t
w(rst)L
LOW-level reset time 4 - 4 - ns
t
rst
reset time SDA clear 500 - 500 - ns
t
REC;STA
recovery time to START condition 0 - 0 - ns
