13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
Applies to 3.3V and 5V.
NOTES:
1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2. Actual value depends on clock period.
3. If #47 is satisfied for both DT
ACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4. For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
5. If the asynchronous input setup time (#47) requirement is satisfied for DT
ACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6. When AS
and R/W are equally loaded (
±
20%), subtract 5 ns from the values given in these columns.
7. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
NUM CHARACTERISTIC
10MHz 16MHz 20MHz
UNIT
MIN MAX MIN MAX MIN MAX
29 AS
, LDS, UDS Negated to Data-In Invalid (Hold Time on Read) 0—0—0—ns
29A AS
, LDS, UDS Negated to Data-In High Impedance (Read) — 150 — 90 — 75 ns
30 AS
, LDS, UDS Negated to BERR Negated 0—0—0—ns
31
2,5
DTACK
Asserted to Data-In Valid (Setup Time on Read) — 65 — 50 — 42 ns
32 HALT
and RESET Input Transition Time 0 150 0 150 0 150 ns
33 Clock High to BG
Asserted — 35 — 30 — 25 ns
34 Clock High to BG
Negated — 35 — 30 — 25 ns
35 BR
Asserted to BG Asserted 1.5 3.5 1.5 3.5 1.5 3.5 Clks
36
7
BR
Negated to BG Negated 1.5 3.5 1.5 3.5 1.5 3.5 Clks
38 BG
Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
—55—50—42ns
39 BG
Width Negated 1.5 — 1.5 — 1.5 — Clks
44 AS
, LDS, UDS Negated to AVEC Negated 0 55 0 50 0 42 ns
47
5
Asynchronous Input Setup Time 5—5—5—ns
48
2,3
BERR
Asserted to DTACK Asserted 20 — 10 — 10 — ns
52 Data-In Hold from Clock High 0—0—0—ns
53 Data-Out Hold from Clock High (Write) 0—0—0—ns
55 R/W
Asserted to Data Bus Impedance Change (Write) 20 — 10 — 0 — ns
56
4
HALT, RESET Pulse Width 10 — 10 — 10 — Clks
58
7
BR
Negated to AS, LDS, UDS, R/W Driven 1.5 — 1.5 — 1.5 — Clks
58A
7
BR
Negated to FC Driven 1—1—1—Clks
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
