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TC7109ACKW

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
TC7109/A
DS21456D-page 4 2002-2012 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Positive Supply Voltage (GND to V+)..................+6.2V
Negative Supply Voltage (GND to V-) .....................-9V
Analog Input Voltage (Low to High)
(Note 1)
.... V+ to V-
Reference Input Voltage:
(Low to High) (Note 1) ............................. V+ to V-
Digital Input Voltage:
(Pins 2-27) (Note 2)...........................GND – 0.3V
Power Dissipation, T
A
< 70°C (Note 3)
CERDIP ......................................................2.29W
Plastic DIP ..................................................1.23W
PLCC ..........................................................1.23W
PQFP ..........................................................1.00W
Operating Temperature Range
Plastic Package (C) .........................0°C to +70°C
Ceramic Package (I) .....................-25°C to +85°C
Storage Temperature Range..............-65°C to +150°C
*Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
TC7109/TC7109A ELECTRICAL SPECIFICATIONS
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, T
A
= +25°C, unless otherwise indicated.
Symbol Parameter Min Typ Max Unit Test Conditions
Analog
Overload Recovery Time (TC7109A) — 0 1 Measurement
Cycle
Zero Input Reading -0000
8
±0000
8
+0000
8
Octal Reading V
IN
= 0V; Full Scale = 409.6mV
Ratio Metric Reading 3777
8
3777
8
4000
8
4000
8
Octal Reading V
IN
= V
REF
V
REF
= 204.8mV
NL Non-Linearity (Max Deviation
from Best Straight Line Fit)
-1 ±0.2 +1 Count Full Scale = 409.6mV to 2.048V
Over Full Operating
Temperature Range
Rollover Error (Difference in Reading for
Equal Positive and Inputs near
(Full Scale)
-1 ±0.02 +1 Count Full Scale = 409.6mV to
2.048V Over Full Operating
Temperature Range
CMRR Input Common Mode
Rejection Ratio
—50 — V/V V
CM
±1V, V
IN
= 0V
Full Scale = 409.6mV
V
CMR
Common Mode Voltage Range V- +1.5 — V+ -1.5 V Input High, Input Low and
Common Pins
e
N
Noise (P-P Value Not
Exceeded 95% of Time)
—15 — VV
IN
= 0V, Full Scale = 409.6mV
I
IN
Leakage Current at Input — 1 10 pA V
IN
, All Packages: +25°C
— 20 100 pA C Device: 0°C T
A
+70°C
— 100 250 pA I Device: -25°C T
A
+85°C
TC
ZS
Zero Reading Drift — 0.2 1 V/°C V
IN
= 0V
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
2002-2012 Microchip Technology Inc. DS21456D-page 5
TC7109/A
TC
FS
Scale Factor Temperature Coefficient — 1 5 V/°C V
IN
= 408.9mV = >7770
8
Reading, Ext Ref = 0ppm/°C
I
+
Supply Current (V+ to GND) — 700 1500 AV
IN
= 0V, Crystal Oscillator
3.58MHz Test Circuit
I
S
Supply Current (V+ to V-) — 700 1500 A Pins 2-21, 25, 26, 27, 29 Open
V
REF
Reference Out Voltage -2.4 -2.8 -3.2 V Referenced to V+, 25k
Between V+ and Ref Out
TC
REF
Ref Out Temperature Coefficient — 80 — ppm/°C 25k Between V+ and Ref Out
0°C T
A
+70°C
Digital
V
OH
Output High Voltage
I
OUT
= 700A
3.5 4.3 — V TC7109: I
OUT
= 100A
Pins 3 -16, 18, 19, 20
TC7109A: I
OUT
= 700A
V
OL
Output Low Voltage — 0.2 0.4 AI
OUT
= 1.6mA
Output Leakage Current — ±0.01 ±1 A Pins 3 -16 High-Impedance
Control I/O Pull-up Current — 5 — F Pins 18, 19, 20 V
OUT
= V+ – 3V
Mode Input at GND
Control I/O Loading — — 50 pF HBEN
, Pin 19; LBEN, Pin 18
V
IH
Input High Voltage 2.5 — — V Pins 18 -21, 26, 27
Referenced to GND
V
IL
Input Low Voltage — — 1 V Pins 18-21, 26, 27
Referenced to GND
Input Pull-up Current —
—
5
25
—
—
A
A
Pins 26, 27; V
OUT
= V+
– 3V
Pins 17, 24; V
OUT
= V+ – 3V
Input Pull-down Current — 1 — A Pins 21, V
OUT
= GND = +3V
Oscillator Output Current, High — 1 — mA V
OUT
– 2.5V
Oscillator Output Current, Low — 1.5 — mA V
OUT
– 2.5V
Buffered Oscillator Output Current High — 2 — mA V
OUT
– 2.5V
Buffered Oscillator Output Current Low — 5 — mA V
OUT
– 2.5V
t
W
Mode Input Pulse Width 60 — — nsec
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package
and store only in conductive foam, antistatic tubes, or other conducting material. Use proper antistatic handling pro-
cedures. Do not connect in circuits under “power-on” conditions, as high transients may cause permanent damage.
TC7109/TC7109A ELECTRICAL SPECIFICATIONS (Continued)
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, T
A
= +25°C, unless otherwise indicated.
Symbol Parameter Min Typ Max Unit Test Conditions
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
TC7109/A
DS21456D-page 6 2002-2012 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
(40-Pin PDIP)
Symbol Description
1 GND Digital ground, 0V, ground return for all digital logic.
2 STATUS Output HIGH during integrate and de-integrate until data is latched. Output LOW when
analog section is in auto-zero or zero integrator configuration.
3 POL Polarity – High for positive input.
4 OR Over Range – High if over ranged (Three-State Data bit).
5B
12
Bit 12 (Most Significant bit) (Three-State Data bit).
6B
11
Bit 11 (Three-State Data bit).
7B
10
Bit 10 (Three-State Data bit).
8B
9
Bit 9 (Three-State Data bit).
9B
8
Bit 8 (Three-State Data bit).
10 B
7
Bit 7 (Three-State Data bit).
11 B
6
Bit 6 (Three-State Data bit).
12 B
5
Bit 5 (Three-State Data bit).
13 B
4
Bit 4 (Three-State Data bit).
14 B
3
Bit 3 (Three-State Data bit).
15 B
2
Bit 2 (Three-State Data bit).
16 B
1
Bit 1 (Least Significant bit) (Three-State Data bit).
17 TEST Input High – Normal operation. Input LOW – Forces all bit outputs HIGH.
Note: This input is used for test purposes only.
18 LBEN
Low Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates low order byte outputs, B
1
–B
8
. With MODE (Pin 21) HIGH, this pin serves as
low byte flag output used in Handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)
19 HBEN
High Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates high order byte outputs, B
9
–B
12
, POL, OR. With MODE (Pin 21) HIGH, this
pin serves as high byte flag output used in Handshake mode. See Figures 3-7, 3-8, and 3-9.
20 CE
/LOAD Chip Enable/Load – with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable.
When HIGH, B
1
–B
12
, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load
strobe is used in handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)
21 MODE Input LOW – Direct Output mode where CE
/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin
18) act as inputs directly controlling byte outputs. Input Pulsed HIGH - Causes immediate
entry into Handshake mode and output of data as in Figure 3-9.
Input HIGH – enables CE
/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs,
Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9
at conversions completion.
22 OSC IN Oscillator Input.
23 OSC OUT Oscillator Output.
24 OSC SEL Oscillator Select – Input HIGH configures OSC IN, OSC OUT, BUFF OSC OUT as RC
oscillator – clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW
configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency
at BUFF OSC OUT.
25 BUFF OSC OUT Buffered Oscillator Output.
26 RUN/HOLD
Input HIGH – Conversions continuously performed every 8192 clock pulses.
Input LOW – Conversion in progress completed; converter will stop in auto-zero seven
counts before integrate.
27 SEND Input - Used in Handshake mode to indicate ability of an external device to accept data.
Connect to V+ if not used.
28 V- Analog Negative Supply – Nominally -5V with respect to GND (Pin 1).
29 REF OUT Reference Voltage Output – Nominally 2.8V down from V+ (Pin 40).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

TC7109ACKW

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Buy TC7109ACKW
Manufacturer:
Microchip Technology
Description:
Analog to Digital Converters - ADC 13 Bit Fast Recovery
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