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EP9301-CQZR
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
DS636F2
Copyright 201
0 Cirrus Logic (A
ll Rights Reser
ved)
25
EP9301
Entry Level ARM9
System-on-Chip Pr
ocessor
S
tatic Memory Single W
rite W
ait Cycle
Parameter
Symbol
Min
T
yp
Max
Unit
W
AIT to WRn deassert delay time
t
WRd
t
HCLK
×
2
-
t
HCLK
×
4
ns
CSn assert to W
AIT time
t
WAI
T
d
--
t
HCLK
×
(WST1-2)
ns
W
AIT assert time
t
WAI
Tp
w
t
HCLK
×
2
-
t
HCLK
×
510
ns
W
AIT to CSn deassert delay time
t
CSnd
t
HCLK
×
3
-
t
HCLK
×
5
ns
Figure 13. Static Memory Singl
e Write Wait Cycle Timing Measurement
CSn
WRn
RDn
DQMn
AD
DA
WAIT
t
WAITpw
t
WAITd
t
CSnd
t
WRd
26
Copyright 20
10 Cirrus Logi
c (All Rights Rese
rved)
DS636F2
EP9301
Entry Level ARM9 System-on-Chip Proces
sor
S
tatic Memory T
urnaround Cycle
Notes:
1. X and Y represent any two chip select numbers.
2. IDCY occurs on read-to-write and write-to-read.
3. IDCY is honored when going from a asynchronous
device (CSx) to
a sync
hronous device (/SDCSy).
Parameter
Sy
mbol
Min
T
yp
Max
Unit
CSnX deassert to CSnY assert time
t
BT
cyc
-
t
HCLK
×
(IDCY+1)
-n
s
Figure 14. Static Memory Turnaround
Cycle Timing Measurement
AD
CSnX
WRn
RDn
DQMn
DA
CSnY
t
BTcyc
WAIT
DS636F2
Copyright 201
0 Cirrus Logic (A
ll Rights Reser
ved)
27
EP9301
Entry Level ARM9
System-on-Chip Pr
ocessor
Ethernet MAC Interface
ST
A - S
tation - Any device that conta
ins an IEEE 802.1
1
conforming Medium Access Control (MAC) and physical layer
(PHY) interface to the wirele
ss medium.
PHY - Ethernet physical layer interface.
Parameter
Symbol
Min
T
yp
Max
Unit
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
10 Mbit
mode
100 Mbit
mode
TXCLK cycle time
t
TX_per
--
4
0
0
4
0
--
n
s
TXCLK high time
t
TX_high
140
14
200
20
260
26
ns
TXCLK lo
w time
t
TX_low
140
14
200
20
260
26
ns
TXCLK to signal transition delay time
t
TXd
0
0
10
10
25
25
ns
TXCLK rise/fall time
t
TXrf
----
5
5
n
s
RXCLK cycle time
t
RX_per
--
4
0
0
4
0
--
n
s
RXCLK high time
t
RX_high
140
14
200
20
260
26
ns
RXCLK low time
t
RX_low
140
14
200
20
260
26
ns
RXDV
AL / RXERR setup time
t
RXs
1
0
1
0
----
n
s
RXDV
AL / RXERR hold time
t
RXh
1
0
1
0
----
n
s
RXCLK rise/fall time
t
RXrf
----
5
5
n
s
MDC cycle time
t
MDC_per
--
4
0
0
4
0
0
--
n
s
MDC high time
t
MDC_high
1
6
0
1
6
0
----
n
s
MDC lo
w time
t
MDC_low
1
6
0
1
6
0
----
n
s
MDC rise/fall time
t
MDCrf
----
5
5
n
s
MDIO setup time (ST
A sourced)
t
MDIOs
1
0
1
0
----
n
s
MDIO hold time (ST
A sourced)
t
MDIOh
1
0
1
0
----
n
s
MDC to MDIO signal transition delay time
(PHY sourced)
t
MDIOd
----
3
0
0
3
0
0
n
s
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
EP9301-CQZR
Mfr. #:
Buy EP9301-CQZR
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Entry-Level ARM9 SOC Processor
Lifecycle:
New from this manufacturer.
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