MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 9
BIT
PD1, PD0
0
D7, D6
PD1 and PD0 select the various clock and power-down modes.
Full Power-Down Mode. Clock mode is unaffected.
D5 ACQMOD
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
NAME FUNCTIONAL DESCRIPTION
0
10
Standby Power-Down Mode. Clock mode is unaffected.
0
11
Normal Operation Mode. External clock mode selected.
1
Normal Operation Mode. Internal clock mode selected.
D4
SGL/DIF
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2, 4).
D3
UNI/BIP
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V
REF
can be converted; in bipolar mode, the
signal can range from -V
REF
/2 to +V
REF
/2.
D2, D1, D0 A2, A1, A0
Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted
(Tables 2, 3).
Table 1. Control-Byte Functional Description
the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. At the
end of the acquisition interval, the T/H switch opens,
retaining charge on C
HOLD
as a sample of the signal
at IN+.
The conversion interval begins with the input multiplex-
er switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at
the comparator’s positive input. The capacitive digital-
to-analog converter (DAC) adjusts during the remain-
Figure 3a. MAX1295 Simplified Input Structure Figure 3b. MAX1297 Simplified Input Structure
IN- CHANNEL.
