AD9831ASTZ-REEL Datasheet AD9831ASTZ, AD9831ASTZ-REEL, EVAL-AD9831EBZ | P1-P3

EVAL-AD9831EB

FEATURES

Full-Featured Evaluation Board for the AD9831

Various Linking Options

PC Software for Control of AD9831

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source via a BNC connector. Latches (74HC574) are also on

the board, these latches being used to hold the 16-bit data

word being written from the PC to the AD9831.

OPERATING THE AD9831 EVALUATION BOARD

Power Supplies

This evaluation board has two analog power supply inputs:

AVDD and AGND. AVDD equals +5 V or +3.3 V and is

used to provide the AVDD for the AD9831. DGND and

DVDD connections are also available. The DVDD is used to

provide the DVDD for the AD9831, the 25 MHz oscillator

and the DVDD for the logic chips. DGND and AGND are

connected at the AD9831. Therefore, it is recommended not

to connect AGND and DGND elsewhere in the system.

All power supplies are decoupled to ground. AVDD and

DVDD are decoupled using 10µF tantalum capacitors and

0.1µF ceramic capacitors at the input to the evaluation board.

The power supplies are again decoupled using 0.1µF capaci-

tors at the AD9831, the crystal and the logic.

Evaluation Board for the AD9831

Direct Digital Synthesizer

INTRODUCTION

This Application Note describes the evaluation board for the

AD9831 Direct Digital Synthesizer (DDS). The AD9831 is a

numerically controlled oscillator employing a phase accumula-

tor, a sine look-up table and a 10-bit D/A converter. The

part can be operated with clock frequencies up to 25 MHz.

Both phase modulation and frequency modulation can be per-

formed with the AD9831. Full data on the AD9831 is avail-

able in the AD9831 datasheet available from Analog Devices

and should be consulted in conjunction with this Application

Note when using the evaluation board.

The evaluation board interfaces to the parallel port of an IBM

compatible PC. Software is available with the evaluation

board which allows the user to easily program the AD9831.

Components on the AD9831 Evaluation Board include a 25

MHz oscillator which provides the MCLK for the AD9831.

The user can remove this oscillator, if required, and drive the

AD9831 with a different clock oscillator or an external clock

Evaluation Board Setup

Parallel Port Centronics

Printer Cable

IBM Compatible PC

AD9831.EXE

AD9831 Evaluation

Board

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EVAL-AD9831EB

Link and Switch Options

There are five link options which must be set for the required operating setup before using the evaluation board. The functions

of these options are outlined below.

Link No. Function

LK1 The PSEL1 input can be controlled by the user via a BNC connector or, alternatively, by switch SW.

When LK1 is arranged so that PSEL1 is connected to SW, the user can control the PSEL1 signal using the

double throw switch.

Alternatively, PSEL1 can be tied to a BNC connector by altering LK1 so that the user can provide the PSEL1

control from a logic source.

LK2 The PSEL0 input can be controlled by the user via a BNC connector or, alternatively, by switch SW.

When LK2 is arranged so that PSEL0 is connected to SW, the user can control the PSEL0 signal using the

double throw switch.

Alternatively, PSEL0 can be tied to a BNC connector by altering LK2 so that the user can provide the PSEL0

control from a logic source.

LK3 The FSELECT input can be controlled by the user via a BNC connector or, alternatively, by switch SW.

When LK3 is arranged so that FSELECT is connected to SW, the user can control the FSELECT signal using

the double throw switch.

Alternatively, FSELECT can be tied to a BNC connector by altering LK3 so that the user can provide the

FSELECT control from a logic source.

LK4 LK4 is used to place the AD9831 in sleep mode.

When LK4 is connected so that

SLEEP is tied to DGND, the AD9831 is placed in sleep mode whereby the

AD9831's internal clocks, REFOUT and the DAC are disabled.

When LK4 is connected so that

SLEEP is tied to DVDD, the AD9831 is powered up.

LK5 The reference to the AD9831 can be provided by the on-board reference, which is available at REFOUT, or an

external reference of nominal value 1.21 V can be used. When LK5 is closed, the on-board reference is used.

When this link is opened, REFIN is disconnected from REFOUT and the reference can be provided by the

user via a BNC connector.

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Preliminary Technical Data AD7002

EVAL-AD9831EB

36-Way Connector Pin Description

DGND Digital Ground. These lines are connected

to the digital ground plane on the evaluation

board.

DB0 - DB7 Data Bit 0 to Data Bit 7. Data transfers

from the PC are 8 bits wide. Therefore, the

16 bit word is split into two 8 bit words.

For each write operation, there are 3 trans-

fers of data from the PC: the 8 MSBs of the

16 bit word, the 8 LSBs of the 16 bit word

and the address data to bits A0, A1 and A2.

The AD9831 accepts CMOS logic.

LOAD When the 8 MSBs of the 16 bit word are

written to the evaluation board from the PC,

the word is held in a latch, a 74HC574 latch.

This latch latches in the data on the rising

edge of the CK signal. The LOAD signal

provides this rising edge.

LATCH The 8 LSBs of the 16 bit word are held in

the latch U3. The rising CK edge to this

part is provided by LATCH.

WR Write. This is an active low logic input

which is used to write the digital data to the

AD9831. When the address bits A0, A1 and

A2 are being written to, the

WR signal is

generated also. On the rising edge of

WR,

the AD9831 reads in the 16 bit word from

the 74HC574 latches along with the address

values.

RESET Reset. When RESET is taken low, the

AD9831 is reset. On reset, the phase accu-

mulator is reset to zero.

SET-UP CONDITIONS

Care should be taken before applying power and signals to the

evaluation board to ensure that all link positions are as per the

required operating mode. Table 1 shows the position in which

all the links are set when the evaluation board is sent out.

Table 1. Initial Link and Switch Positions

Link No. Function

LK1 LK1 is arranged so that PSEL1 is tied to

SW.

LK2 LK2 is arranged so that PSEL0 is tied to

SW.

LK3 LK3 is arranged so that FSELECT is tied to

SW.

LK4 LK4 is connected so that

SLEEP is tied to

DVDD and, hence, the AD9831 is powered

up.

LK5 REFOUT is tied to REFIN.

SW All the SW switches are arranged so that

DVDD is selected.

EVALUATION BOARD INTERFACING

Interfacing to the evaluation board is via a 36-way centronics

female connector, J1. The pinout for the J1 connector is

shown in Figure 1 and its pin designations are given in Table

Figure 1. Pin Configuration for the 36-Way Connector, J1.

P1-P3 P4-P6 P7-P7

AD9831ASTZ-REEL

Mfr. #:

Buy AD9831ASTZ-REEL

Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized Direct Digital Synthesizer

Lifecycle:

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AD9831ASTZ-REEL

AD9831ASTZ-REEL

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