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X90100M8IZ

P1-P3P4-P6P7-P7
4
FN8156.0
February 2, 2005
AC Timing
Notes: (6) MI in the A.C. timing diagram refers to the minimum incremental change in the C
TOTAL
output due to a change in the counter value.
(7) t
IH
+ t
IL
4µs
Endurance and Data Retention V
CC
= 5V, T
A
= 25°C unless otherwise specified
PARAMETER MIN UNIT
Minimum endurance 100,000 Data changes per bit
Data retention 100 Years
AC Conditions of Test
Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input reference levels 1.5V
AC Electrical Specifications V
CC
= 5V, T
A
= 25°C unless otherwise specified.
SYMBOL PARAMETER MIN TYP
(4)
MAX UNIT
t
Cl
CS to INC setup 100 ns
t
lD
INC HIGH to U/D change 100 ns
t
DI
U/D to INC setup 100 ns
t
lL
(7)
INC
LOW period 1 µs
t
lH
(7)
INC
HIGH period 1 µs
t
lC
INC Inactive to CS inactive 1 µs
t
CPHNS
(5)
CS
Deselect time (NO STORE) 1 µs
t
CPHS
(5)
CS
Deselect time (STORE) 10 ms
t
IW
INC to C
TOTAL
change 1 5 µs
t
CYC
INC cycle time 4 µs
t
R,
t
F
(5)
INC
input rise and fall time 500 µs
t
PU
(5)
Power up to capacitance stable 5 µs
t
R
V
CC
(5)
V
CC
power-up rate 0.2 50 V/ms
t
WR
(5)
Store cycle 510ms
CS
INC
U/D
C
TOTAL
t
CI
t
IL
t
IH
t
CYC
t
ID
t
IW
MI
(6)
t
IC
t
CPHS
t
F
t
R
10%
90% 90%
(Store)
t
DI
t
CPHNS
X90100
5
FN8156.0
February 2, 2005
Power Up Timing (Digital Inputs Floating, Internal Pullup Action Shown)
Power Up and Down Requirements
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the Cp, Cm
pins provided that V
CC
is always more positive than or equal
to V
Cp
, V
Cm
, i.e., V
CC
V
Cp
, V
Cm
. The V
CC
ramp rate spec
is always in effect.
Powerup Requirements
In order to prevent unwanted tap position changes or an
inadvertant store, bring the CS
and INC high before or
concurrently with the V
CC
pin. The logic inputs have internal
active pullups to provide reliable powerup operation. See
powerup timing diagram.
Pin Configuration
Detailed Pin Descriptions
Cp and Cm
The high (Cp) and low (Cm) terminals of the X90100 are
equivalent to the fixed terminals of a mechanical trimmable
capacitor. The minimum dc voltage is V
SS
and the maximum
is V
CC
. The value of capacitance across the terminals is
determined by digital inputs INC
, U/D, and CS.
Up/Down (U/D)
The U/D input controls the direction of the trimmed capacitor
value and whether the counter is incremented or
decremented. This pin has an active current source pullup.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the capacitance value and either increment or
decrement the counter in the direction indicated by the logic
level on the U/D
input. This pin has an active current source
pullup.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS
is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X90100 will be placed in
the low power standby mode until the device is selected
once again. This pin has active circuit source pullup.
N/C - This pin should be left floating.
Principles of Operation
There are three sections of the X90100: the input control,
counter and decode section; the nonvolatile memory; and
the capacitor array. The input control section operates just
like an up/down counter. The output of this counter is
decoded to turn on electronic switches connecting internal
units to the sum capacitor. Under the proper conditions the
contents of the counter can be stored in nonvolatile memory
V
CC
CS
INC
U/D
V
CC
= 3.3 or 5.0V
t
R
V
CC
V
CC
CS
INC
U/D
1
2
3
4
8
7
6
5
X90100
MSOP
N/C (leave floating)
Cm
Vss
Cp
Pin Names
SYMBOL DEFAULT DESCRIPTION
Cp output Positive capacitor terminal
Cm output Negative capacitor terminal
V
SS
supply Ground
V
CC
supply Positive supply voltage
U/D
pull up Up/Down control input
INC
pull up Increment control input
CS
pull up Chip Select control input
X90100
6
FN8156.0
February 2, 2005
and retained for future use. The capacitor array is comprised
of 31 individual capacitors connected in parallel. At one end
of each element is an electronic switch that connects it to the
sum.
The capacitor, when at either end of the range, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the counter changes positions. If
the counter is moved several positions, multiple units are
connected to the total for t
IW
(INC to C
TOTAL
change). The
C
TOTAL
value for the device can temporarily be increased by
a significant amount if the counter is moved several
positions.
When the device is powered-down, the last counter position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the capacitor is set to the value last stored.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
capacitor total value. With CS
set LOW the device is
selected and enabled to respond to the U/D
and INC inputs.
HIGH to LOW transitions on INC
will increment or decrement
(depending on the state of the U/D
input) a five bit counter.
The output of this counter is decoded to select one of thirty
two capacitor combinations for the capacitor array.
The value of the counter is stored in nonvolatile memory
whenever CS
transitions HIGH while the INC input is also
HIGH.
The system may select the X90100, move the capacitor
value and deselect the device without having to store the
latest count total in nonvolatile memory. After the count
movement is performed as described above and once the
new position is reached, the system must keep INC
LOW
while taking CS
HIGH. The new C
TOTAL
value will be
maintained until changed by the system or until a power-
up/down cycle recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments can be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D
may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the counter up and down until the proper trim is
attained.
Table of Values
Mode Selection
CS INC U/D MODE
L H Cap Value Up
L L Cap Value Down
H X Store Cap Position
H X X Standby Current
L X No Store, Return To Standby
L H Cap Value Up (not recommended)
L L Cap Value Down (not recommended)
X90100
P1-P3P4-P6P7-P7

X90100M8IZ

Mfr. #:
Buy X90100M8IZ
Manufacturer:
Renesas / Intersil
Description:
IC DIGITAL CAPACITOR 8MSOP
Lifecycle:
New from this manufacturer.
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