74LVT_LVTH244A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 April 2013 3 of 15
NXP Semiconductors
74LVT244A-Q100; 74LVTH244A-Q100
3.3 V octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration for SO20 and TSSOP20 Fig 4. Pin configuration for DHVQFN20
/97+$4
2( 9
&&
$ 2(
< <
$ $
< <
$ $
< <
$ $
< <
*1' $
DDD
DDD
/97$4
/97+$4
<
$
<
$
< <
$ $
< <
$ $
< <
$ 2(
*1'
*1'
$
2(
9
&&
Table 2. Pin description
Symbol Pin Description
1OE
, 2OE 1, 19 output enable input (active low)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input
2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 data output
GND 10 ground (0 V)
2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input
1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output
V
CC
20 supply voltage