NCP3030A, NCP3030B, NCV3030A, NCV3030B
www.onsemi.com
12
CURRENT LIMIT AND CURRENT LIMIT SET
Overview
The NCP3030 uses the voltage drop across the High Side
MOSFET during the on time to sense inductor current. The
I
Limit
block consists of a voltage comparator circuit which
compares the differential voltage across the V
CC
Pin and the
V
SW
Pin with a resistor settable voltage reference. The sense
portion of the circuit is only active while the HS MOSFET
is turned ON.
CONTROL
Vset
6
RSet
Iset
13 uA
DAC /
COUNTER
Ilim Out
HSDR
LSDR
VSW
VIN
VCC
Itrip Ref
VSense
Switch
Cap
Figure 25. I
set
/ I
Limit
Block Diagram
Itrip Ref−63 Steps, 6.51 mV/step
Current Limit Set
The I
Limit
comparator reference is set during the startup
sequence by forcing a typically 13 mA current through the
low side gate drive resistor. The gate drive output will rise
to a voltage level shown in the equation below:
V
set
+ I
set
*R
set
(eq. 1)
Where I
SET
is 13 mA and R
SET
is the gate to source resistor
on the low side MOSFET.
This resistor is normally installed to prevent MOSFET
leakage from causing unwanted turn on of the low side
MOSFET. In this case, the resistor is also used to set the
I
Limit
trip level reference through the I
Limit
DAC. The I
set
process takes approximately 350 ms to complete prior to
Soft−Start stepping. The scaled voltage level across the I
SET
resistor is converted to a 6 bit digital value and stored as the
trip value. The binary I
Limit
value is scaled and converted to
the analog I
Limit
reference voltage through a DAC counter.
The DAC has 63 steps in 6.51 mV increments equating to a
maximum sense voltage of 403 mV. During the I
set
period
prior to Soft−Start, the DAC counter increments the
reference on the I
SET
comparator until it crosses the V
SET
voltage and holds the DAC reference output to that count
value. This voltage is translated to the I
Limit
comparator
during the I
Sense
portion of the switching cycle through the
switch cap circuit. See Figure 25. Exceeding the maximum
sense voltage results in no current limit. Steps 0 to 10 result
in an effective current limit of 0 mV.
Current Sense Cycle
Figure 26 shows how the current is sampled as it relates
to the switching cycle. Current level 1 in Figure 26
represents a condition that will not cause a fault. Current
level 2 represents a condition that will cause a fault. The
sense circuit is allowed to operate below the 3/4 point of a
given switching cycle. A given switching cycle’s 3/4 T
on
time is defined by the prior cycle’s T
on
and is quantized in
10 ns steps. A fault occurs if the sensed MOSFET voltage
exceeds the DAC reference within the 3/4 time window of
the switching cycle.
