AQD-SD3L8GE16-MG Datasheet AQD-SD3L8GE16-MG | P7-P9

tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address

bus inputs are SWITCHING; Data pattern is same as IDD4W

IDD1 756 mA

Precharge power

down

current

;

All banks idle; tCK = tCK(IDD); CKE is

LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

IDD2P 324 mA

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is

HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus

inputs are FLOATING

IDD2Q 576 mA

Precharge sta

ndby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH,

/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING

IDD2N 576 mA

Active power

down current;

All banks open; tCK = tCK(IDD); CKE is LOW;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

IDD3P 684 mA

Active standby current;

All banks open; tCK = tCK(IDD), tRAS =

tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING

IDD3N 684 mA

Operating burst read current;

All banks open, Continuous burst reads, IOUT

= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),

tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address

bus inputs are SWITCHING; Data pattern is same as IDD4W

IDD4R 1575 mA

Operating burst write current;

All banks open, Continuous burst writes; BL =

8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);

CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING IDD4R

IDD4W 1287 mA

Burst refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD)

interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD5 2277 mA

Self refresh current;

CK and /CK at 0V; CKE 0.2V; Other control and

address bus inputs are FLOATING; Data bus inputs are FLOATING

IDD6 360 mA

Operating

bank interleave read current;

All bank interleaving reads, IOUT =

0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =

tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH

between valid commands;Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4R;

IDD7 2142 mA

Note: 1.Module I

was calculated on the specific brand DRAM(3xnm) component I

and can be differently

measured according to DQ loading capacitor.

Timing Parameters & Specifications

204Pin DDR3 1.35V 1600 ECC SODIMM

8GB Based on 512Mx8

AQD-SD3L8GE16-MG

Speed DDR3 1600 Unit

Parameter Symbol Min Max

Average Clock Period

tCK 8 - ns

CK high-level width

tCH 0.47 0.53 tCK

CK low-level width tCL 0.47 0.53 tCK

DQS, /DQS to DQ skew, per group,

per access

tDQSQ - 100 ps

DQ output hold time from DQS, /DQS

tQH 0.38 - tCK

DQ low-impedance time from CK, /CK

tLZ(DQ) -450 225

DQ high-impedance time from CK,

/CK

tHZ(DQ) - 225

Data setup time to DQS, /DQS

reference to Vih(ac)Vil(ac) levels

tDS

(AC135)

25 - ps

Data hold time to DQS, /DQS

reference to Vih(ac)Vil(ac) levels

tDH

(DC90)

DQ and DM input pulse width for each

input

tDIPW 360 - ps

DQS, /DQS Read preamble

tRPRE 0.9 - tCK

DQS, /DQS differential Read

postamble

tRPST 0.3 - tCK

DQS, /DQS Write preamble

tWPRE 0.9 - tCK

DQS, /DQS Write postamble

tWPST 0.3 - tCK

DQS, /DQS low-impedance time

tLZ(DQS) -450 225 ps

DQS, /DQS high-impedance time

tHZ(DQS)

- 225 ps

DQS, /DQS differential input low pulse

width

tDQSL 0.45 0.55 tCK

DQS, /DQS differential input high

pulse width

tDQSH 0.45 0.55 tCK

DQS, /DQS rising edge to CK, /CK

rising edge

tDQSS -0.27 0.27 tCK

DQS, /DQS falling edge setup time to

CK, /CK rising edge

tDSS

0.18 -

tCK

DQS, /DQS falling edge hold time to

CK, /CK rising edge

tDSH 0.18 - tCK

Delay from start of Internal write

transaction to Internal read command

tWTR

Max

(4tck, 7.5ns)

Write recovery time tWR

15 -

Mode register set command cycle

time

tMRD 4 - tCK

/CAS to /CAS command delay

tCCD

4 - tCK

Auto precharge write recovery +

precharge time

tDAL

tWR+tRP/tCK tCK

Active to active command period for

tRRD Max - ns

204Pin DDR3 1.35V 1600 ECC SODIMM

8GB Based on 512Mx8

AQD-SD3L8GE16-MG

1KB page size

(4tck, 7.5ns)

Speed DDR3 1600 Unit

Parameter Symbol Min Max

Active to active command period for

2KB page size

tRRD

Max

(4tck, 6ns)

Four Activate Window for 1KB page

size

tFAW 30 - ns

Power-up and RESET calibration time

tZQinitl

512 - tCK

Normal operation Full calibration time

tZQoper

256 -

tCK

Normal operation short calibration

time

tZQcs 64

- tCK

Exit self refresh to commands not

requiring a locked DLL

tXS

Max

(5tCK, tRFC+10ns)

Exit self refresh to commands

requiring a locked DLL

tXSDLL

tDLL(min) - tCK

Internal read to precharge command

delay

tRTP

Max

(4tck, 7.5ns)

Minimum CKE low width for Self

refresh entry to exit timing

tCKESR tCK(min)+1tCK

Exit power down with D

LL to any valid

command: Exit Precharge Power

Down with DLL

tXP

Max

(3tCK, 6ns)

CKE minimum pulse width (high and

low pulse width)

tCKE

Max

(3tCK, 5ns)

Asynchronous RTT turn-on delay

(Power-Down mode)

tAONPD 2 8.5

Asynchronous RTT turn-off delay

(Power-Down mode)

tAOFPD

2 8.5 ns

ODT turn-on tAON -225 225

ODT turn-off tAOF 0.3 0.7

tCK

P1-P3 P4-P6 P7-P9 P10-P11

AQD-SD3L8GE16-MG

Mfr. #:

Buy AQD-SD3L8GE16-MG

Manufacturer:

Advantech

Description:

Memory Modules 8G ECC SO-DDR3-1600 1.35V 512X8 MIC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

AQD-SD3L8GE16-MG