RT8204BGQW Datasheet RT8204BGQW | P13-P15

RT8204B

DS8204B-04 April 2011 www.richtek.com

The switching waveforms may appear noisy and

asynchronous when light loading causes diode-emulation

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-off in DEM noise

vs. light-load efficiency is made by varying the inductor

value. Generally, low inductor values produce a broader

efficiency vs. load curve, while higher values result in higher

full-load efficiency (assuming that the coil resistance

remains fixed) and less output voltage ripple. The

disadvantages for using higher inductor values include

larger physical size and degrades load-transient response

(especially at low input-voltage levels).

Forced-CCM Mode (EN/DEM = floating)

The low noise, forced-CCM mode (EN/DEM = floating)

disables the zero-crossing comparator, which controls the

low side switch on-time. This causes the low side gate-

drive waveform to become the complement of the high

side gate-drive waveform. This in turn causes the inductor

current to reverse at light loads as the PWM loop to

maintain a duty ratio V

OUT

. The benefit of forced-CCM

mode is to keep the switching frequency fairly constant,

but it comes at a cost: The no-load battery current can be

up to 10mA to 40mA, depending on the external

MOSFETs.

Current Limit Setting (OCP)

The RT8204B has cycle-by-cycle current limiting control.

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at OC is above the current limit threshold, the PWM

is not allowed to initiate a new cycle (Figure 2).

L, peak

LIM

Load

Figure 2. Valley Current-Limit

Current sensing of the RT8204B can be accomplished in

two ways. Users can either use a current sense resistor

or the on-state of the low side MOSFET (R

DS(ON)

). For

resistor sensing, a sense resistor is placed between the

source of low side MOSFET and PGND (Figure 3(a)).

DS(ON)

sensing is more efficient and less expensive (Figure

3(b)). There is a compromise between current limit

accuracy and sense resistor power dissipation.

ILIM

LGATE

PHASE

ILIM

LGATE

PHASE

Figure 3. Current Sense Methods

(a)

(b)

In both cases, the R

ILIM

resistor between the OC pin and

PHASE pin sets the over current threshold. This resistor

ILIM

is connected to a 20μA current source within the

RT8204B which is turned on when the low side MOSFET

turns on. When the voltage drop across the sense resistor

or low side MOSFET equals the voltage across the R

ILIM

resistor, positive current limit will be activated. The high

side MOSFET will not be turned on until the voltage drop

across the sense element (resistor or MOSFET) falls

below the voltage across the R

ILIM

resistor.

Choose a current limit resistor by following equation :

ILIM

= I

LIMIT

x R

SENSE

/ 20μA

Carefully observe the PC board layout guidelines to ensure

that noise and DC errors do not corrupt the current sense

signal seen by OC and PGND. Mount the IC close to the

low side MOSFET and sense resistor with short, direct

traces, making a Kelvin sense connection to the sense

resistor.

RT8204B

DS8204B-04 April 2011www.richtek.com

MOSFET Gate Driver (UGATE, LGATE)

The high side driver is designed to drive high current, low

DS(ON)

N-MOSFETs. When configured as a floating driver,

5V bias voltage is delivered from VDDP supply. The average

drive current is proportional to the gate charge at

= 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

BOOT and PHASE pins.

A dead time to prevent shoot through is internally

generated between high side MOSFET off to low side

MOSFET on, and low side MOSFET off to high side

MOSFET on.

The low side driver is designed to drive high current, low

DS(ON)

N-MOSFETs. The internal pull-down transistor that

drives LGATE low is robust, with a 0.6Ω typical on-

resistance. A 5V bias voltage is delivered form VDDP

supply. The instantaneous drive current is supplied by the

flying capacitor between VDDP and PGND.

For high current applications, some combinations of high

and low side MOSFETs might be encountered that will

cause excessive gate-drain coupling, which can lead to

efficiency-killing, EMI-producing shoot-through currents.

This is often remedied by adding a resistor in series with

BOOT, which increases the turn-on time of the high side

MOSFET without degrading the turn-off time (Figure 4).

BOOT

UGATE

PHASE

+5V

Figure 4. The UGATE Rise Time Reduction

Power Good Output (PGOOD)

The power good output is an open-drain output and requires

a pull-up resistor. When the output voltage is 15% above

or 10% below its set voltage, the PGOOD gets pulled

low. It is held low until the output voltage returns to within

these tolerances once more. In soft start, the PGOOD is

actively held low and is allowed to be pulled high until soft

start is over and the output reaches 93% of its set voltage.

There is a 2.5μs delay built into the PGOOD circuitry to

prevent false transition.

POR, UVLO and Soft-Start

Power On Reset (POR) occurs when VDD rises above to

approximately 4.3V, the RT8204B will reset the fault latch

and prepare the PWM for operation. If the VDD is below

4.1V

(MIN)

, the VDD undervoltage lockout (UVLO) circuitry

inhibits switching by keeping UGATE and LGATE low.

A built-in soft-start is used to prevent the surge current

from power supply input after EN/DEM is enabled. It

clamps the ramping of internal reference voltage which is

compared with the FB signal. The typical soft-start duration

is 1.35ms.

Furthermore, the maximum allowed current limit is

segment in 2 steps during 1.35ms period.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage protection. When the output voltage exceeds 15%

of the its setting voltage threshold, the over voltage

protection is triggered and the low side MOSFET is latched

on. This activates the low side MOSFET to discharge the

output capacitor.

The RT8204B is latched once OVP is triggered and can

only be released by VDD or EN/DEM power on reset. There

is a 20μs delay built into the over voltage protection circuit

to prevent false transitions.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. When the output voltage is less than

70% of its set voltage threshold, the under voltage

protection is triggered and then both UGATE and LGATE

gate drivers are forced low. In order to remove the residual

charge on the output capacitor during the under voltage

period, if the PHASE is greater than 1V, the LGATE is

forced high until PHASE is lower than 1V. There is 2.5μs

delay built into the under voltage protection circuit to

prevent false transitions. During the soft-start, the UVP

will be blanked around 3.1ms.

Output Voltage Setting (FB)

The output voltage can be adjusted from 0.75V to 3.3V by

setting the feedback resistor R1 and R2 (Figure 5). Choose

R2 to be approximately 10kΩ, and solve for R1 using the

equation:

RT8204B

DS8204B-04 April 2011 www.richtek.com

OUT FB

V = V 1

⎡⎤

⎛⎞

×+

⎜⎟

⎢⎥

⎝⎠

⎣⎦

where V

is 0.75V.

Note that in order for the device to regulate in a controlled

manner, the ripple content at the feedback pin, V

, should

be approximately 15mV at minimum V

BAT

, and worst case

no smaller than 10mV. If V

ripple

at minimum V

BAT

is less

than 15mV, the above component values should be

revisited in order to improve this. Quite often a small

capacitor, C1, is required in parallel with the top feedback

resistor, R1, in order to ensure that V

is large enough.

The value of C1 can be calculated as follows, where R2 is

the bottom feedback resistor.

Firstly calculating the value of Z1 required :

()

ripple_VBAT(MIN)

Z1 = V 0.015

0.015

×−Ω

Secondly calculating the value of C1 required to achieve

this :

(

)

SW_VBAT(MIN)

Z1 R1

C1 = F

−

××

Finally using the equation as follows to verify the value of

FB_VBAT(MIN) ripple_VBAT(MIN)

SW_VBAT(MIN)

V = V

R2+

2f C1

⎡⎤

⎢⎥

+×× ×

⎣⎦

where V

ripple_VBAT(MIN)

is the output ripple voltage in

minimum V

BAT

;

sw_VBAT(MIN)

is the switching frequency in minimum V

BAT

;

FB_VBAT(MIN)

is the ripple voltage into FB pin in minimum

BAT

PHASE

BOOT

OUT

UGATE

VOUT

GND

Figure 5. Setting The Output Voltage

For application that output voltage is higher than 3.3V,

user can also use a voltage divider to keep VOUT pin

voltage within 0.75V to 2.8V as shown in Figure 6. For

this case, T

can be determined as below :

TON OUT_FB

TON ON

TON OUT_FB

TON ON

If R < 2M then T = 3.85p

V0.5

R V

If R 2M then T = 3.55p

V0.4

Ω×

−

≥Ω ×

−

Where R

TON

is T

set resistor and the V

OUT_FB

is the

output signal of resistor divider. Since the switching

frequency is

OUT

IN ON

F =

VT×

For a given switching frequency, we can obtain the R

TON

as below

TON

OUT OUT

TON

IN OUT_FB S

TON

OUT OUT

TON

IN OUT_FB S

If R < 2M then

V0.5V

R =

V V F 3.85p

If R 2M then

V0.4V

R =

V V F 3.55p

−

××

≥Ω

−

××

Figure 6. Output Voltage Setting for V

OUT

> 3.3V

Application

PHASE

BOOT

OUT

UGATE

VOUT

GND

VIN

TON

OUT_FB

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or L

) determine the inductor value as follows :

ON IN OUT

IR LOAD(MAX)

T(V - V)

L =

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

RT8204BGQW

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