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AD5530BRUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD5530/AD5531
Rev. B | Page 4 of 20
V
DD
= 12 V ± 10%; V
SS
= −12 V ± 10%; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
AD5530 AD5531 Unit Test Conditions/Comments
ACCURACY
Resolution 12 14 Bits
Relative Accuracy ±1 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature
Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Gain Error ±1 ±4 LSB typ
Gain Temperature Coefficient
2
0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max
REFERENCE INPUTS
2
Reference Input Range 0 to 4.096 0 to 4.096 V min to V max Max output range ±8.192 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ±1 μA max Per input, typically ±20 nA
DUTGND INPUT
2
DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range −3 to +3 −3 to +3 V min to V max Max output range ±8.192 V
O/P CHARACTERISTICS
2
Output Voltage Swing ±8.192 ±8.192 V max
Short-Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max
DIGITAL I/O
V
INH
, Input High Voltage 2.4 2.4 V min
V
INL
, Input Low Voltage 0.8 0.8 V max
I
INH
, Input Current ±10 ±10 μA max Total for all pins
C
IN
, Input Capacitance
2
10 10 pF max 3 pF typical
SDO V
OL
, Output Low Voltage 0.4 0.4 V max I
SINK
= 1 mA
POWER REQUIREMENTS
V
DD
/V
SS
+12/−12 +12/−12 V nom ±10% for specified performance
Power Supply Sensitivity
ΔFull Scale/ΔV
DD
110 110 dB typ
ΔFull Scale/ΔV
SS
100 100 dB typ
I
DD
2 2 mA max Outputs unloaded
I
SS
2 2 mA max Outputs unloaded
I
DD
in Power-Down 150 150 μA max Typically 50 μA
1
Temperature range for B Version: −40°C to +85°C.
2
Guaranteed by design, not subject to production test.
AD5530/AD5531
Rev. B | Page 5 of 20
AC PERFORMANCE CHARACTERISTICS
V
DD
= 10.8 V to 16.5 V, V
SS
= −10.8 V to −16.5 V; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 3.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 20 μs typ
Full-scale change to ±½ LSB. DAC latch contents alternately
loaded with all 0s and all 1s.
Slew Rate 1.3 V/μs typ
Digital-to-Analog Glitch Impulse 120 nV-s typ
DAC latch alternately loaded with 0x0FFF and 0x1000. Not
dependent on load conditions.
Digital Feedthrough 0.5 nV-s typ Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 1 kHz 100 nV/√Hz typ All 1s loaded to DAC.
STANDALONE TIMING CHARACTERISTICS
V
DD
= 10.8 V to 16.5 V, V
SS
= −10.8 V to −16.5 V; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
1, 2
f
MAX
7 MHz max SCLK frequency
t
1
140 ns min SCLK cycle time
t
2
60 ns min SCLK low time
t
3
60 ns min SCLK high time
t
4
50 ns min
SYNC to SCLK falling edge setup time
t
5
40 ns min
SCLK falling edge to
SYNC rising edge
t
6
50 ns min
Min
SYNC high time
t
7
40 ns min Data setup time
t
8
15 ns min Data hold time
t
9
5 ns min
SYNC high to LDAC low
t
10
50 ns min
LDAC pulse width
t
11
5 ns min
LDAC high to SYNC low
t
12
50 ns min
CLR
pulse width
1
Guaranteed by design, not subject to production test.
2
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with t
R
= t
F
= 5 ns (10% to
90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
SCLK
SYNC
SDIN
MSB
DB15 DB14 DB11 DB0
LSB
t
1
t
3
t
2
t
5
t
4
t
6
t
7
t
8
t
9
t
10
t
11
t
12
LDAC
1
CLR
1
LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED.
0
0938-002
Figure 2. Timing Diagram for Standalone Mode
AD5530/AD5531
Rev. B | Page 6 of 20
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
V
DD
= 10.8 V to 16.5 V, V
SS
= −10.8 V to −16.5 V; GND = 0 V; R
L
= 5 kΩ and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 5.
Parameter Limit at T
MIN
, T
MAX
Unit Description
1, 2, 3
f
MAX
2 MHz max SCLK frequency
t
1
500 ns min SCLK cycle time
t
2
200 ns min SCLK low time
t
3
200 ns min SCLK high time
t
4
50 ns min
SYNC to SCLK falling edge setup time
t
5
40 ns min
SCLK falling edge to
SYNC rising edge
t
6
50 ns min
Min
SYNC high time
t
7
40 ns min Data setup time
t
8
15 ns min Data hold time
t
12
50 ns min
CLR pulse width
t
13
130 ns min SCLK falling edge to SDO valid
t
14
50 ns max SCLK falling edge to SDO invalid
t
15
50 ns min
RBEN to SCLK falling edge setup time
t
16
50 ns min
RBEN hold time
t
17
100 ns min
RBEN falling edge to SDO valid
1
Guaranteed by design, not subject to production test.
2
Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with t
R
= t
F
= 5 ns (10% to
90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
SDO; R
PULLUP
= 5 kΩ, C
L
= 15 pF
00938-003
SCLK
SYNC
SDIN
SDO
(DAISY-
CHAINING)
RBEN
SDO
(READBACK)
MSB
DB15 DB14 DB11 DB0
DB15 DB11 DB0
LSB
MSB LSB
MSB LSB
RB0RB1300
t
1
t
3
t
2
t
5
t
4
t
6
t
7
t
8
t
13
t
14
t
15
t
16
t
13
t
14
t
17
Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5530BRUZ

Mfr. #:
Buy AD5530BRUZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-BIT VTG OUTPUT IC
Lifecycle:
New from this manufacturer.
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