Detailed Description
The MAX5820 is a dual, 8-bit, voltage-output DAC with
an I
2
C/SMBus™-compatible 2-wire interface. The
device consists of a serial interface, power-down cir-
cuitry, dual input and DAC registers, two 8-bit resistor
string DACs, two unity-gain output buffers, and output
resistor networks. The serial interface decodes the
address and control bits, routing the data to the proper
input or DAC register. Data can be directly written to
the DAC register, immediately updating the device out-
put, or can be written to the input register without
changing the DAC output. Both registers retain data as
long as the device is powered.
DAC Operation
The MAX5820 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5820’s
input coding is straight binary, with the output voltage
given by the following equation:
where N = 8 (bits) and D = the decimal value of the
input code (0 to 255).
Output Buffer
The MAX5820 analog outputs are buffered by precision,
unity-gain followers that slew 0.5V/µs. Each buffer output
swings rail-to-rail, and is capable of driving 5k in parallel
with 200pF. The output settles to ±0.5 LSB within 4µs.
Power-On Reset
The MAX5820 features an internal POR circuit that ini-
tializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered down,
with the output buffers disabled and the outputs pulled
to GND through the 100k termination resistor.
Following power-up, a wake-up command must be initi-
ated before any conversions are performed.
Power-Down Modes
The MAX5820 has three software-controlled low-power
power-down modes. All three modes disable the output
buffers and disconnect the DAC resistor strings from
REF, reducing supply current draw to 1µA and the ref-
erence current draw to less than 1µA. In power-down
mode 0, the device output is high impedance. In
power-down mode 1, the device output is internally
pulled to GND by a 1k termination resistor. In power-
down mode 2, the device output is internally pulled to
GND by a 100k termination resistor. Table 1 shows
the power-down mode command words.
Upon wake-up, the DAC output is restored to its previ-
ous value. Data is retained in the input and DAC regis-
ters during power-down mode.
Digital Interface
The MAX5820 features an I
2
C/SMBus-compatible 2-
wire interface consisting of a serial data line (SDA) and
a serial clock line (SCL). The MAX5820 is SMBus com-
patible within the range of V
DD
= 2.7V to 3.6V. SDA and
SCL facilitate bidirectional communication between the
MAX5820 and the master at rates up to 400kHz. Figure
1 shows the 2-wire interface timing diagram. The
MAX5820 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5820 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (S
r
) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
V
VD
OUT
REF
N
_ =
×
2
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1V
DD
Power Supply
2 GND Ground
3 ADD Address Select. A logic-high sets the address LSB to 1; a logic-low sets the address LSB to zero.
4 SCL Serial Clock Input
5 SDA Bidirectional Serial Data Interface
6 REF Reference Input
7 OUTA DAC A Output
8 OUTB DAC B Output
SMBus is a trademark of Intel Corporation.
MAX5820
The MAX5820 SDA and SCL drivers are open-drain out-
puts, requiring a pullup resistor to generate a logic high
voltage (see the Typical Operating Circuit). Series
resistors R
S
are optional. These series resistors protect
the input stages of the MAX5820 from high-voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the I
2
C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA, while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5820. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see the
Acknowledge Bit (ACK) section). The STOP condition
frees the bus. If a repeated START condition (Sr) is
generated instead of a STOP condition, the bus
remains active. When a STOP condition or incorrect
address is detected, the MAX5820 internally discon-
nects SCL from the serial interface until the next START
condition, minimizing digital noise and feedthrough.
Early STOP Conditions
The MAX5820 recognizes a STOP condition at any
point during transmission except if a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I
2
C format; at
least one clock pulse must separate any START and
STOP conditions.
Repeated START Conditions
A repeated START (S
r
) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S
r
may also be used when the bus
master is writing to several I
2
C devices and does not
want to relinquish control of the bus. The MAX5820 seri-
al interface supports continuous write operations with or
without an S
r
condition separating them. Continuous
read operations require S
r
conditions because of the
change in direction of data flow.
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
8 _______________________________________________________________________________________
POWER-DOWN
COMMAND BITS
PD1 PD0
MODE/FUNCTION
00
Power-up device. DAC output
restored to previous value.
01
Power-down mode 0. Power down
device with output floating.
10
Power-down mode 1. Power down
device with output terminated with
1k to GND.
11
Power-down mode 2. Power down
device with output terminated with
100k to GND.
Table 1. Power-Down Command Bits
SCL
SDA
STOP
CONDITION
START
CONDITION
REPEATED START CONDITIONSTART CONDITION
t
LOW
t
SU, DAT
t
SU, STA
t
SP
t
BUF
t
HD, STA
t
SU, STO
t
F
t
HD, STA
t
HIGH
t
HD, DAT
t
R
Figure 1. 2-Wire Serial-Interface Timing Diagram
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5820 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5820 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address (Figure 4). When idle, the MAX5820
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit-by-bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or read-
ing from the MAX5820 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5820 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5820 has four different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
DD
sets A0 = 1. This feature allows up to four
MAX5820s to share the same bus.
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5820 (Figure 5). Bits C3–C0 con-
figure the MAX5820 (Table 3). Bits D7–D0 are DAC
data. Bits S3–S0 are sub-bits and are always 0. Input
and DAC registers update on the falling edge of SCL
during the acknowledge bit. Should the write cycle be
prematurely aborted, data is not updated and the write
cycle must be repeated. Figure 6 shows two example-
write data sequences.
Extended Command Mode
The MAX5820 features an extended command mode
that is accessed by setting C3–C0 = 1 and D7–D4 = 0.
MAX5820
Dual, 8-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________ 9
SCL
SDA
SS
r
P
Figure 2. START and STOP Conditions
SCL
SDA
STOP START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION
Figure 3. Early STOP Conditions
S A6A5A4A3A2A1A0
R/W
Figure 4. Slave-Address Byte Definition
C3 C2 C1 C0 D7 D6 D5 D4
Figure 5. Command-Byte Definition
PART V
ADD
DEVICE ADDRESS
(A6–A0)
MAX5820L GND 0111 000
MAX5820L V
DD
0111 001
MAX5820M GND 1011 000
MAX5820M V
DD
1011 001
Table 2. MAX5820 I
2
C Slave Addresses

MAX5820MEUA+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 8-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet