ISL29004IROZ-T7 Datasheet ISL29004IROZ-T7 | P7-P9

FN6221.0

December 21, 2006

Command Register 00(hex)

The Read/Write command register has five functions:

(1) Enable; Bit 7.This function either resets the ADC or

enables the ADC in normal operation. A logic 0 disables

ADC to reset-mode. A logic 1 enables adc to normal

operation.

(2) AdcPD; Bit 6. This function puts the device in a power

down mode. A logic 0 puts the device in normal operation. A

logic 1 powers down the device.

(3) Timing Mode; Bit 5. This function determines whether the

integration time is done internally or externally. In Internal

Timing Mode, integration time is determined by an internal

dual speed oscillator (fosc), and the n-bit (n = 4, 8, 12,16)

counter inside the ADC. In External Timing Mode, integration

time is determined by the time between two consecutive

external-sync sync_iic pules commands.

(4) Photodiode Select Mode; Bits 3 and 2. This function

controls the mux attached to the two photodiodes. At Mode0,

the mux directs the current of Diode1 to the ADC. At Mode1,

the mux directs the current of Diode2 only to the ADC.

Mode3 is a sequential Mode0 and Mode1 with an internal

subtract function (Diode1 - Diode2).

* n = 4, 8, 12,16 depending on the number of clock cycles

function.

(5) Width; Bits 1 and 0. This function determines the number

of clock cycles per conversion. Changing the number of

clock cycles does more than just change the resolution of

the device. It also changes the integration time, which is the

period the device’s analog-to-digital (A/D) converter samples

the photodiode current signal for a Lux measurement.

Control Register 01(hex)

The Read/Write control register has three functions:

(1) Interrupt flag; Bit 5. This is the status bit of the interrupt.

The bit is set to logic high when the interrupt thresholds have

been triggered, and logic low when not yet triggered. Writing

a logic low clears/resets the status bit.

(2) Range/Gain; Bits 3 and 2. The Full Scale Range can be

adjusted by an external resistor Rext and/or it can be

adjusted via I2C using the Gain/Range funtion. Gain/Range

has four possible values, Range(k) where k is 1 through 4.

Table 9 lists the possible values of Range(k) and the

resulting FSR for some typical value R

EXT

resistors. When

Gain/Range is set to Range1 or Range2, the fosc runs at

327kHz. When Gain/Range is set to Range3 or Range4 fosc

runs at twice the rate at 655kHz. The automatic fosc

adjustment feature improves signal-to-noise ratio for low Lux

measurements.

TABLE 2. WRITE ONLY REGISTERS

ADDRESS

NAME

FUNCTIONS/

DESCRIPTION

b1xxx_xxxx sync_iic Writing a logic 1 to this address bit ends

the current adc-integration and starts

another. Used only with External Timing

Mode.

bx1xx_xxxx clar_int Writing a logic 1 to this address bit

clears the interrupt.

TABLE 3. ENABLE

BIT 7 OPERATION

0 Disable ADC-core to reset-mode (default)

1 Enable ADC-core to normal operation

TABLE 4. adcPD

BIT 6 OPERATION

0 Normal operation (default)

1 Power Down

TABLE 5. TIMING MODE

BIT 5 OPERATION

0 Internal Timing Mode. Integration time is internally

timed determined by fosc, REXT, and number of clock

cycles.

1 External Timing Mode. Integration time is externally

timed by the I2C host.

TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3

BITS 3:2 MODE

0:0 Mode0. ADC integrates or converts Diode1 only. Current

is converted to an n-bit unsigned data.*

0:1 Mode1. ADC integrates or coverts Diode2 only. Current is

converted to an n-bit unsigned data.*

1:0 MODE3. A sequential Mode0 then Mode1 operation. The

difference current is an (n-1) signed data.*

1:1 No operation.

TABLE 7. WIDTH

BITS 1:0 NUMBER OF CLOCK CYCLES

0:0 2^16 = 65,536

0:1 2^12 = 4,096

1:0 2^8 = 256

1:1 2^4 = 16

TABLE 8. INTERRUPT FLAG

BIT 5 OPERATION

0 Interrupt is cleared or not triggered yet

1 Interrupt is triggered

ISL29004

FN6221.0

December 21, 2006

Interrupt persist; Bits 1 and 0. The interrupt pin and the

interrupt flag is triggered/set when the data sensor reading is

out of the interrupt threshold window after m consecutive

number of integration cycles. The interrupt persist bits

determine m.

Interrupt Threshold HI Register 02(hex)

This register sets the the HI threshold for the interrupt pin

and the interrupt flag. By default the Interrupt threshold HI is

FF(hex). The 8-bit data written to the register represents the

upper MSB of a 16-bit value. The LSB is always 00(hex).

Interrupt Threshold LO Register 03(hex)

This register sets the the LO threshold for the interrupt pin

and the interrupt flag. By default the Interrupt threshold LO is

00(hex). The 8-bit data written to the register represents the

upper MSB of a 16-bit value. The LSB is always 00(hex).

Sensor Data Register 04(hex) and 05(hex)

When the device is configured to output a 16-bit data, the

most significant byte is accessed at 04(hex), and the least

significant byte can be accessed at 05(hex). The sensor data

Timer Data Register 06(hex) and 07(hex)

Note that the timer counter value is only available when

using the External Timing Mode. The 06(hex) and 07(hex)

are the LSB and MSB respectively of a 16-bit timer counter

value corresponding to the most recent sensor reading.

Each clock cycle increments the counter. At the end of each

integration period, the value of this counter is made available

over the I

C. This value can be used to eliminate noise

introduced by slight timing errors caused by imprecise

external timing. Microcontrollers, for example, often cannot

provide high-accuracy command-to-command timing, and

the timer counter value can be used to eliminate the

resulting noise.

Calculating Lux

The ISL29004’s output codes, DATA, are directly

proportional to Lux.

The proportionality constant α is determined by the Full

Scale Range, FSR, and the n-bit ADC which is user defined

in the command register. The proportionality constant can

also be viewed as the resolution; The smallest Lux

measurement the device can measure is α.

Full Scale Range, FSR, is determined by the software

programmable Range/Gain, Range(k), in the command

EXT

which is

referenced to 100kΩ.

The transfer function effectively for each timing mode

becomes:

INTERNAL TIMING MODE

EXTERNAL TIMING MODE

n = 4, 8, 12, or 16. This is the number of clock cycles

programmed in the command register.

Range(k) is the user defined range in the Gain/Range bit

in the command register.

EXT

is an external scaling resistor hardwired to the R

EXT

pin.

DATA is the output sensor reading in number of counts

available at the data register.

represents the maximum number of counts possible in

Internal Timing Mode. For the External Timing Mode the

TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES

BITS

3:2 k RANGE(k)

FSR LUX

RANGE@

EXT

= 100k

FSR LUX

RANGE@

EXT

= 50k

FSR LUX

RANGE@

EXT

= 500k

0:0 1 973 973 1946 195

0:1 2 3892 3892 7784 778

1:0 3 15,568 15,568 31,136 3114

1:1 4 62,272 62,272 124,544 12,454

TABLE 10. INTERRUPT PERSIST

BITS 1:0 NUMBER OF INTEGRATION CYCLES

0:0 1

0:1 4

1:0 8

1:1 16

TABLE 11. DATA REGISTERS

ADDRESS

(hex) CONTENTS

04 Least-significant byte of most recent sensor reading.

05 Most-significant byte of most recent sensor reading.

06 Least-significant byte of timer counter value

corresponding to most recent sensor reading.

07 Most-significant byte of timer counter value

corresponding to most recent sensor reading.

E α DATA×=

(EQ. 1)

FSR

------------

(EQ. 2)

(EQ. 3)

FSR Range k()

100kΩ

EXT

------------------

×=

(EQ. 4)

Range k()

100kΩ

EXT

------------------

----------------------------------------------------

DATA×=

(EQ. 5)

Range k()

100kΩ

EXT

------------------

COUNTER

----------------------------------------------------

DATA×=

ISL29004

FN6221.0

December 21, 2006

maximum number of counts is stored in the data register

named COUNTER

COUNTER is the number increments accrued for between

integration time for External Timing Mode.

Gain/Range, Range(k)

The Gain/Range can be programmed in the control register

to give Range (k) determining the FSR. Note that Range(k)

is not the FSR. See Equation 3. Range(k) provides four

constants depending on programmed k that will be scaled by

EXT

. See Table 9. Unlike R

EXT

, Range(k) dynamically

adjusts the FSR. This function is especially useful when light

conditions are varying drastically while maintaining excellent

resolution.

Number of Clock Cycles, n-bit ADC

The number of clock cycles determines “n” in the n-bit ADC; 2

clock cycles is a n-bit ADC. n is programmable in the command

good balance of speed, and resolution has to be considered

when deciding for n. For fast and quick measurement, choose

the smallest n = 4. For maximum resolution without regard of

time, choose n = 16. Table 12 compares the tradeoff between

integration time and resolution. See Equations 10 and 11 for the

relation between integration time and n. See Equation 3 for the

relation of n and resolution.

External Scaling Resistor R

EXT

and f

osc

The ISL29004 use an external resistor R

EXT

to fix its

internal oscillator frequency, f

osc

. Consequently, R

EXT

determines the fosc, integration time and the FSR of the

device. Fosc, a dual speed mode oscillator, is inversely

proportional to R

EXT

. For user simplicity, the proportionality

constant is referenced to fixed constants 100kΩ and

655kHz:

fosc1 is oscillator frequency when Range1 or Range2 are

set. This is nominally 327kHz when R

EXT

is 100kΩ.

fosc2 is the oscillator frequency when Range3 or Range4

are set. This is nominally 655kHz when R

EXT

is 100kΩ.

When the Range/Gain bits are set to Range1 or Range2,

fosc runs at half speed comapred to when Range/Gain bits

are set to Range3 and Range4.

The automatic fosc adjustment feature allows significant

improvement of signal-to-noise ratio when detecting very low

Lux signals.

Integration Time or Conversion Time

Integration time is the period during which the device’s

analog-to-digital ADC converter samples the photodiode

current signal for a Lux measurement. Integration time, in

other words, is the time to complete the conversion of analog

photodiode current into a digital signal-number of counts.

Integration time affects the measurement resolution. For

better resolution, use a longer integration time. For short and

fast conversions use a shorter integration time.

The ISL29004 offer user flexibility in the integration time to

balance resolution, speed and noise rejection. Integration time

can be set internally or externally and can be programmed in

the command register 00(hex) bit 5.

INTEGRATION TIME IN INTERNAL TIMING MODE

This timing mode is programmed in the command register

00(hex) bit 5. Most applications will be using this timing

mode. When using the Internal Timing Mode, f

osc

and n-bits

resolution determine the integration time. T

int

is a function of

the number of clock cycles and fosc.

n = 4, 8, 12, and16. n is the number of bits of resolution.

therefore is the number of clock cycles. n can be

programmed at the command register 00(hex) bits 1 and 0.

TABLE 12. RESOLUTION AND INTEGRATION TIME

SELECTION

RANGE1

fosc = 327kHz

RANGE4

fosc = 655kHz

TINT (ms)

RESOLUTION

LUX/COUNT

TINT

(ms)

RESOLUTION

(LUX/COUNT)

16 200 0.01 100 1

12 12.8 0.24 6.4 16

8 0.8 3.90 0.4 250

4 0.05 62.5 0.025 4000

EXT

= 100kΩ

(EQ. 6)

osc1

---

100kΩ

EXT

------------------

655× kHz×=

(EQ. 7)

fosc2

100kΩ

EXT

------------------

655× kHz=

(EQ. 8)

osc

---

osc

2()=

int

osc

-------------

×=

(EQ. 9)

For Internal Timing Mode Only

ISL29004

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ISL29004IROZ-T7

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

SENSOR OPT 550NM AMBIENT 8ODFN

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