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74VCXH162373MTX

P1-P3P4-P6P7-P9
© 2005 Fairchild Semiconductor Corporation DS500227 www.fairchildsemi.com
January 2000
Revised June 2005
74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26: Series Resistors in Outputs
74VCXH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26: Series Resistors in Outputs
General Description
The VCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE
) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The VCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The VCXH162373 is also designed with 26
series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
The 74VCXH162373 is designed for low voltage (1.4V to
3.6V) V
CC
applications with output compatibility up to 3.6V.
The 74VCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
■ 1.4V to 3.6V V
CC
supply operation
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ 26 series resistors in outputs
■ t
PD
(I
n
to O
n
)
3.3 ns max for 3.0V to 3.6V V
CC
■ Static Drive (I
OH
/I
OL
)
12 mA @ 3.0V V
CC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model
2000V
Machine model 200V
Ordering Code:
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol Pin Descriptions
Ordering Number
Package
Package Description
Number
74VCXH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74VCXH162373MTX
(Note 1)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
I
0
–I
15
Bushold Inputs
O
0
–O
15
Outputs
www.fairchildsemi.com 2
74VCXH162373
Connection Diagram Truth Tables
H HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial (HIGH or LOW, control inputs may not float)
Z
High Impedance
O
0
Previous O
0
before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCXH162373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the I
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LE
n
is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LE
n
. The
3-STATE outputs are controlled by the Output Enable
(OE
n
) input. When OE
n
is LOW the standard outputs are in
the 2-state mode. When OE
n
is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
LE
1
OE
1
I
0
–I
7
O
0
–O
7
XHXZ
HLL L
HLHH
LLXO
0
Inputs Outputs
LE
2
OE
2
I
8
–I
15
O
8
–O
15
XHXZ
HLL L
HLHH
LLXO
0
3 www.fairchildsemi.com
74VCXH162373
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
(Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
) 0.5V to 4.6V
DC Input Voltage (V
I
) 0.5V to 4.6V
Output Voltage (V
O
)
Outputs 3-STATED
0.5V to 4.6V
Outputs Active (Note 3)
0.5V to V
CC
0.5V
DC Input Diode Current (I
IK
) V
I
0V 50 mA
DC Output Diode Current (I
OK
)
V
O
0V 50 mA
V
O
V
CC
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
) 50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND) 100 mA
Storage Temperature Range (T
STG
) 65 C to 150 C
Power Supply
Operating 1.4V to 3.6V
Input Voltage
0.3V to V
CC
Output Voltage (V
O
)
Output in Active States 0V to V
CC
Output in 3-STATE 0.0V to 3.6V
Output Current in I
OH
/I
OL
V
CC
3.0V to 3.6V 12 mA
V
CC
2.3V to 2.7V 8 mA
V
CC
1.65V to 2.3V 3 mA
V
CC
1.4V to 1.6V 1 mA
Free Air Operating Temperature (T
A
) 40 C to 85 C
Minimum Input Edge Rate (
t/ V)
V
IN
0.8V to 2.0V, V
CC
3.0V 10 ns/V
Symbol Parameter Conditions
V
CC
Min Max Units
(V)
V
IH
HIGH Level Input Voltage 2.7 - 3.6 2.0
V
2.3 - 2.7 1.6
1.65 - 2.3 0.65 x V
CC
1.4 - 1.6 0.65 x V
CC
V
IL
LOW Level Input Voltage 2.7 - 3.6 0.8
V
2.3 - 2.7 0.7
1.65 - 2.3 0.35 x V
CC
1.4 - 1.6 0.35 x V
CC
V
OH
HIGH Level Output Voltage I
OH
100 A 2.7 - 3.6 V
CC
- 0.2
V
I
OH
6 mA 2.7 2.2
I
OH
8 mA 3.0 2.4
I
OH
12 mA 3.0 2.2
I
OH
100 A 2.7 - 3.6 V
CC
- 0.2
I
OH
4 mA 2.3 2.0
I
OH
6 mA 2.3 1.8
I
OH
8 mA 2.3 1.7
I
OH
100 A 1.65 - 2.3 V
CC
- 0.2
I
OH
3 mA 1.65 1.25
I
OH
100 A 1.4 - 1.6 V
CC
- 0.2
I
OH
1 mA 1.4 1.05
P1-P3P4-P6P7-P9

74VCXH162373MTX

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Buy 74VCXH162373MTX
Manufacturer:
ON Semiconductor
Description:
IC LATCH TRANSP 16BIT LV 48TSSOP
Lifecycle:
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