SS-1006-18.1
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Intel Core, Intel Xeon, MAX, Nios, Quartus and Stratix are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.
*Other marks and brands may be claimed as the property of others.
ADDITIONAL DEVELOPMENT TOOLS
TOOLS DESCRIPTION
Intel FPGA SDK for OpenCL
TM
• No additional licenses are required.
• Supported with the Intel Quartus Prime Pro/Standard Edition software.
• The software installation le includes the Intel Quartus Prime Pro/Standard Edition software and the
OpenCL software.
DSP Builder for Intel FPGAs
• Additional licenses are required.
• DSP Builder for Intel FPGAs (Advanced Blockset only) is supported with the Intel Quartus Prime Pro Edition
software for Intel Stratix 10 and Intel Arria 10 devices.
• DSP Builder for Intel FPGAs (Standard Blockset and Advanced Blockset) is supported with the Intel Quartus
Prime Standard Edition software for Intel Arria 10, Stratix V, Arria V, and Cyclone V devices.
Nios
®
II Embedded Design
Suite
• No additional licenses are required.
• Supported with all editions of the Intel Quartus Prime software.
• Includes Nios II software development tools and libraries.
Intel SoC FPGA Embedded
Development Suite (SoC EDS)
• Requires additional licenses for ARM* Development Studio 5* (DS-5*) Intel SoC FPGA Edition.
• The SoC EDS Standard Edition is supported with the Intel Quartus Prime Lite/Standard Edition software
and the SoC EDS Pro Edition is supported with the Intel Quartus Prime Pro Edition software.
INTEL QUARTUS PRIME DESIGN SOFTWARE FEATURES SUMMARY
Enables you to quickly create your I/O design using real time legality checks.
Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs.
Platform Designer
Automates system development by integrating IP functions and subsystems (collection of IP functions) using
a hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture.
Lets you construct your system-level design using IP cores from Intel and from Intel’s third-party IP partners.
Provides expanded language support for System Verilog and VHDL 2008.
Scripting support Supports command-line operation and Tcl scripting, as well as graphical user interface (GUI) design.
Rapid recompile
Maximizes your productivity by reducing your compilation time (for a small design change after a full
compile). Improves design timing preservation.
Incremental optimization
Oers a faster methodology to converge to design sign-o. The traditional tter stage is divided into ner
stages for more control over the design ow.
Partial reconguration
Creates a physical region on the FPGA that can be recongured to execute dierent functions. Synthesize,
place, route, close timing, and generate conguration bitstreams for the functions implemented in the region.
Provides exibility of reusing timing-closed modules or design blocks across projects and teams.
Intel Hyperex
TM
FPGA
Architecture
Provides increased core performance and power eciency for Intel Stratix 10 devices.
Uses post placement and routing delay knowledge of a design to improve performance.
Design space explorer (DSE)
Increases performance by automatically iterating through combinations of Intel Quartus Prime software
settings to nd optimal results.
Provides support for cross-probing between verication tools and design source les.
Provides design-specic advice to improve performance, resource usage, and power consumption.
Chip planner
Reduces verication time while maintaining timing closure by enabling small, post-placement and routing
design changes to be implemented in minutes.
Timing Analyzer
Provides native Synopsys* Design Constraint (SDC) support and allowing you to create, manage, and analyze
complex timing constraints and quickly perform advanced timing verication.
Signal Tap logic analyzer
1
Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering
capabilities available in an embedded logic analyzer.
System Console
Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to
quickly create a GUI to help monitor and send data into your FPGA.
Enables you to analyze and optimize both dynamic and static power consumption accurately.
EDA partners
Oers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-
level simulation, signal integrity analysis, and formal verication. To see a complete list of partners, visit
www.intel.com/fpgaedapartners.
Fractal synthesis
Enables the Intel Quartus Prime software to eciently pack arithmetic operations in FPGA’s logic resources
resulting in signicantly improved performance.
Notes:
1. Available with Talkback feature enabled in the Intel Quartus Prime Lite Edition software.
Getting Started Steps
Step 1: Download the free Intel Quartus Prime Lite Edition software
www.intel.com/quartus
Step 2: Get oriented with the Intel Quartus Prime software interactive tutorial
After installation, open the interactive tutorial on the welcome screen.
Step 3: Sign up for training
www.intel.com/fpgatraining
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
