LTC3568
13
3568fa
applicaTions inForMaTion
the losses in LTC3568 circuits: 1) LTC3568 V
IN
current,
2) switching losses, 3) I
2
R losses, 4) other losses.
1. The V
IN
current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small loss
that increases with V
IN
, even at no load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current
out of V
IN
that is typically much larger than the DC bias
current. In continuous mode, I
GATECHG
= f
O
(QT + QB),
where QT and QB are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V
IN
and thus their effects
will be more pronounced at higher supply voltages.
3. I
2
R Losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2(R
SW
+ RL)
4. Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
Thermal
Considerations
In a majority of applications, the LTC3568 does not dis-
sipate much heat due to its high efficiency. However, in
applications where the LTC3568 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3568 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3568 is in
dropout at an input voltage of 3.3V with a load current of
1.8A with a 70°C ambient temperature. From the Typical
Performance Characteristics graph of Switch Resistance,
the R
DS(ON)
resistance of the P-channel switch is 0.125Ω.
Therefore, power dissipated by the part is:
P
D
= I
2
• R
DS(ON)
= 405mW
The DFN package junction-to-ambient thermal resistance,
θ
JA
is 43°C/W. Therefore, the junction temperature of the
regulator operating in a 70°C ambient temperature is
approximately:
T
J
= 0.405 • 43 + 70 = 87.4°C
Remembering that the above junction temperature is
obtained from an R
DS(ON)
at 70°C, we might recalculate
the junction temperature based on a higher R
DS(ON)
since
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
LTC3568
14
3568fa
applicaTions inForMaTion
Design Example
As a design example, consider using the LTC3568 in a typical
application with V
IN
= 5V. The load requires a maximum
of 1.8A in active mode and 10mA in standby mode. The
output voltage is V
OUT
= 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the timing resistor:
R MHz k
T
=
( )
=
9 78 10 1 323 8
11
1 08
. .
.
Use a standard value of 324k. Next, calculate the inductor
value for about 40% ripple current at maximum V
IN
:
L
V
MHz mA
V
V
H=
= µ
2 5
1 720
1
2 5
5
1 7
.
.
.
Choosing the closest inductor from a vendor of 2µH,
results in a maximum ripple current of:
Δ =
µ
=I
V
MHz
V
V
mA
L
2 5
1 2
1
2 5
5
625
.
.
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C
A
MHz V
F
OUT
= µ2 5
1 8
1 5 2 5
36.
.
( % . )
The closest standard value is 22µF plus 10µF. Since the
supplys output impedance is very low, C
IN
is typically a
22µF. In noisy environments, decoupling SV
IN
from PV
IN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the LTC3568 is with a 13kΩ and 1000pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires
a pull-up resistor. A 100k resistor is used for adequate
speed.
Figure 1 shows the complete schematic for this design
example.
Board
Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3568. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
Figure 6. LTC3568 Layout Diagram (See Board Layout Checklist)
PV
IN
LTC3568
PGND
SW
SV
IN
SGND
PGOODPGOOD
V
FB
SYNC/MODE
I
TH
SHDN/R
T
L1
V
IN
BMPS
V
IN
V
OUT
R5
R
T
R3R1R2
3568 F06
C3
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
C
OUT
C4
LTC3568
15
3568fa
applicaTions inForMaTion
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 6) and power GND (Pin 5) as close as possible?
This capacitor provides the AC current to the internal
power MOSFETs and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate
of C
OUT
returns current to PGND and the (–) plate
of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line ter-
minated near SGND (Pin 3). The feedback signal V
FB
should be routed away from noisy components and
traces, such as the SW line (Pin 4), and its trace should
be minimized.
4.
Keep sensitive components away from the SW pin. The
input capacitor C
IN
, the compensation capacitor C
C
and
C
ITH
and all the resistors R1, R2, R
T
, and R
C
should be
routed away from the SW trace and the inductor L1.
5. A
ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND pin.
6. Flood
all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to one of the input supplies: PV
IN
, PGND,
SV
IN
or SGND.
SV
IN
LTC3568
PGOOD PGOOD
SW
PV
IN
SYNC/MODE V
FB
I
TH
SHDN/R
T
SGND
L1
2µH
V
IN
2.5V TO
5.5V
V
OUT
1.8V/2.5V/3.3V
AT 1.8A
R5
100k
R4
324k
R1A
280k
R3
13k
RS1
1M
BM
RS2
1M
3568 F07a
C3
1000pF
C4 22pF
R2 887K
C2
22µF
x2
SGND SGND
R1B
412k
R1C
698k
PS
FC
PGND
C1
22µF
PGND
PGNDSGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A915AY-2ROM (D53LC SERIES)
GND
3.3V 2.5V 1.8V
LOAD CURRENT (mA)
EFFICIENCY (%)
100
95
90
85
80
75
70
1 100 1000 10000
3568 F07b
10
V
IN
= 3.3V
V
OUT
= 2.5V
CIRCUIT OF FIGURE 7
Burst Mode
OPERATION
PULSE SKIP
FORCED CONTINUOUS
Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors
Efficiency vs Load Current
Typical applicaTions

LTC3568EDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.8A, 4MHz, Sync Buck DC/DC Conv
Lifecycle:
New from this manufacturer.
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