LTC1064
3
1064fb
ELECTRICAL CHARACTERISTICS
(Complete Filter) The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at V
S
= ±5V, T
A
= 25°C, TTL clock input level, unless otherwise specified.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Center Frequency Range, f
O
V
S
= ±8V, Q ≤ 3 0.1 to 140 kHz
Input Frequency Range 0 to 1 MHz
Clock-to-Center Frequency LTC1064 f
CLK
= 1MHz, f
O
= 20kHz, Pin 17 High 50 ± 0.3 %
Ratio, f
CLK
/f
O
LTC1064A (Note 2) Sides A, B, C: Mode 1, ● 50 ± 0.8 %
R1 = R3 = 5k, R2 = 5k, Q = 10,
Sides D: Mode 3, R1 = R3 = 50k
● 50 ± 0.9 %
R2 = R4 = 5k
LTC1064 Same as Above, Pin 17 Low, f
CLK
= 1MHz 100 ± 0.3 %
LTC1064A (Note 2) f
O
= 10kHz
Sides A, B, C
● 100 ± 0.8 %
Side D ● 100 ± 0.9
Clock-to-Center Frequency LTC1064 f
CLK
= 1MHz 0.4 %
Ratio, Side-to-Side Matching LTC1064A (Note 2) ● 1%
Clock-to-Center Frequency LTC1064 f
CLK
= 4MHz, f
O
= 80kHz, Pin 17 High 50 ± 0.6 %
Ratio, f
CLK
/f
O
(Note 3) LTC1064A (Note 2) Sides A, B, C: Mode 1, V
S
= ±7.5V 50 ± 1.3 %
R1 = R3 = 50k, R2 = 5k, Q = 5
Side D: Mode 3, R1 = R3 = 50k
R2 = R4 = 5k, f
CLK
= 4MHz
LTC1064 Same as Above, Pin 17 Low 100 ± 0.6 %
LTC1064 A (Note 2) f
CLK
= 4MHz, f
O
= 40kHz 100 ± 1.3 %
Q Accuracy Sides A, B, C: Mode 1, Q = 10
● ±26 %
Side D: Mode 3, f
CLK
= 1MHz ● ±38 %
f
O
Temperature Coefficient Mode 1, 50:1, f
CLK
< 2MHz ±1 ppm/°C
Q Temperature Coefficient Mode 1, 100:1, f
CLK
< 2MHz ±5 ppm/°C
Mode 3, f
CLK
< 2MHz ±5 ppm/°C
DC Offset Voltage V
OS1
(Table 1) f
CLK
= 1MHz, 50:1 or 100:1 ● 215 mV
V
OS2
(Table 1) f
CLK
= 1MHz, 50:1 or 100:1 ● 345 mV
V
OS3
(Table 1) f
CLK
= 1MHz, 50:1 or 100:1 ● 345 mV
Clock Feedthrough f
CLK
< 1MHz 0.2 mV
RMS
Maximum Clock Frequency Mode 1, Q < 5, V
S
≥ ±5V 7 MHz
Power Supply Current 91223 mA
● 26 mA
V
OSN
V
OSBP
V
OSLP
MODE PINS 2, 11, 14, 23 PINS 3, 10, 15, 22 PINS 4, 9, 16, 21
1V
OS1
[(1/Q) + 1 + ⏐⏐ H
OLP
⏐⏐ ] – V
OS3
/Q V
OS3
V
OSN
– V
OS2
1b V
OS1
[(1/Q) + 1 + (R2/R1)] – V
OS3
/Q V
OS3
~(V
OSN
– V
OS2
)[1 + (R5/R6)]
2V
OS1
[(1 + (R2/R1) + (R2/R3) + (R2/R4) – V
OS3
(R2/R3)] V
OS3
V
OSN
– V
OS2
× [R4/(R2 + R4)] + V
OS2
[R2/(R2 + R4)]
3V
OS2
V
OS3
V
OS1
[1 + (R4/R1) + (R4/R2) + (R4/R3)]
– V
OS2
(R4/R2) – V
OS3
(R4/R3)
Table 1. Output DC Offsets, One 2nd Order Section
Note 2: Contact LTC Marketing.
Note 3: Not tested, guaranteed by design.