PCA9671 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 29 September 2011 6 of 33
NXP Semiconductors
PCA9671
Remote 16-bit I/O expander for Fm+ I
2
C-bus with reset
7. Functional description
Refer to Figure 1 “Block diagram of PCA9671”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9671 is shown in Figure 7
. Slave address pins AD2, AD1, and AD0 choose 1 of
64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 3 “
PCA9671 address map”.
Remark: The General Call address (0000 0000) and the Device ID address (1111 100X)
are reserved and cannot be used as device address. Failure to follow this requirement will
cause the PCA9671 not to acknowledge.
Remark: Reserved I
2
C-bus addresses must be used with caution since they can interfere
with:
• “reserved for future use” I
2
C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111)
• slave devices that use the 10-bit addressing scheme (1111 0xx)
• High speed mode (Hs-mode) master code (0000 1xx)
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD2, AD1 and AD0 are held to V
DD
or V
SS
, the same address as the PCF8575 is
applied.
7.1.1 Address maps
Fig 7. PCA9671 address
R/W
002aab636
A6 A5 A4 A3 A2 A1 A0
programmable
slave address
Table 3. PCA9671 address map
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 Address (hex)
V
SS
SCL V
SS
001000020h
V
SS
SCL V
DD
001000122h
V
SS
SDA V
SS
001001024h
V
SS
SDA V
DD
001001126h
V
DD
SCL V
SS
001010028h
V
DD
SCL V
DD
00101012Ah
V
DD
SDA V
SS
00101102Ch
V
DD
SDA V
DD
00101112Eh
