AS7C1025B-15JCN

March 2004
Copyright © Alliance Memory Inc.. All rights reserved.
®
AS7C1025B
5V 128K X 8 CMOS SRAM (Center power and ground)
3/26/04, v. 1.3 Alliance Memory Inc. P. 1 of 9
Features
Industrial and commercial temperatures
Organization: 131,072 x 8 bits
High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
Low power consumption: ACTIVE
- 605mW / max @ 10 ns
Low power consumption: STANDBY
- 55 mW / max CMOS
6 T 0.18 u CMOS technology
Easy memory expansion with
CE
,
OE
inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
ESD protection 2000 volts
Latch-up current 200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C1025B
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 110 100 90 80 mA
Maximum CMOS standby current 10 10 10 10 mA
AS7C1025B
3/26/04, v. 1.3 Alliance Memory Inc. P. 2 of 9
®
Functional description
The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6/7/8 ns are ideal for high-
performance applications. The chip enable input CE
permits easy memory and expansion with multiple-bank memory systems.
When CE
is high, the device enters standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is static, then full
standby power is reached (I
SB1
). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the input pins I/O0 through I/O7 is written on
the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common
industry standard packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
CC
relative to GND V
t1
–0.50 +7.0 V
Voltage on any pin relative to GND V
t2
–0.50 V
CC
+ 0.5 V
Power dissipation P
D
–1.0W
Storage temperature (plastic) T
stg
–65 +150
o
C
Ambient temperature with V
CC
applied T
bias
–55 +125
o
C
DC current into outputs (low) I
OUT
–20mA
Truth table
CE WE OE
Data Mode
H X X High Z Standby (I
SB
, I
SB1
)
L H H High Z Output disable (I
CC
)
LHL D
OUT
Read (I
CC
)
LLX D
IN
Write (I
CC
)
AS7C1025B
3/26/04, v. 1.3 Alliance Memory Inc. P. 3 of 9
®
V
IL
min = -1.0V for pulse width less than 5ns
V
IH
max = V
CC
+2.0V for pulse width less than 5ns.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage V
CC
4.5 5.0 5.5 V
Input voltage
V
IH
2.2 V
CC
+ 0.5 V
V
IL
–0.5 0.8 V
Ambient operating temperature
commercial T
A
0–70
o
C
industrial T
A
–40 85
o
C
DC operating characteristics (over the operating range)
1
Parameter Symbol Test conditions
-10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max
Input leakage current | I
LI
| V
CC
= Max, V
IN
= GND to V
CC
–11–1–1µA
Output leakage
current
| I
LO
|
V
CC
= Max, CE = V
IH
,
V
out
= GND to V
CC
–11–1–1µA
Operating power
supply current
I
CC
V
CC
= Max
CE
V
IL
, f = f
Max,
I
OUT
= 0 mA
110 100 90 80 mA
Standby power supply
current
1
I
SB
V
CC
= Max
CE
V
IH
, f = f
Max
–5045–45–40mA
I
SB1
V
CC
= Max
CE
V
CC
–0.2 V,
V
IN
0.2 V or V
IN
V
CC
–0.2 V,
f = 0
10 10 10 10 mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min 0.4 0.4 0.4 0.4 V
V
OH
I
OH
= –4 mA, V
CC
= Min 2.4 2.4 2.4 2.4 V
Capacitance (f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL)
2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
IN
A,
CE
,
WE
,
OE
V
IN
= 0 V 5 pF
I/O capacitance C
I/O
I/O V
IN
= V
OUT
= 0 V 7 pF

AS7C1025B-15JCN

Mfr. #:
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 5V, 15ns FAST 128K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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