MAX1132BCAP+ Datasheet MAX1133BEAP+, MAX1132BCAP+, MAX1132BEAP+ | P13-P15

the beginning of calibration and goes high to signal the

end of calibration, approximately 80,000 clock cycles

later. In external clock mode, SSTRB goes high at the

beginning of calibration and goes low to signal the end

of calibration. Calibration should be performed in the

same clock mode as will be used for conversions.

Reference

The MAX1132/MAX1133 can be used with an internal

or external reference. An external reference can be

connected directly at the REF pin or at the REFADJ pin.

CREF is an internal reference node and must be

bypassed with a 1µF capacitor when using either the

internal or an external reference.

Internal Reference

When using the MAX1132/MAX1133’s internal refer-

ence, place a 0.22µF ceramic capacitor from REFADJ

to AGND and place a 2.2µF capacitor from REF to

AGND. Fine adjustments can be made to the internal

reference voltage by sinking or sourcing current at

REFADJ. The input impedance of REFADJ is nominally

9kΩ. The internal reference voltage is adjustable to

±1.5% with the circuit of Figure 7.

External reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the MAX1132/

MAX1133’s internal buffer amplifier.

When connecting an external reference to REFADJ, the

input impedance is typically 9kΩ. Using the buffered

REFADJ input makes buffering of the external reference

unnecessary, however, the internal buffer output must

be bypassed at REF with a 2.2µF capacitor.

When connecting an external reference at REF,

REFADJ must be connected to AV

. Then the input

impedance at REF is a minimum of 164kΩ for DC cur-

rents. During conversion, an external reference at REF

must deliver 250µA DC load current and have an out-

put impedance of 10Ω or less. If the reference has a

higher output impedance or is noisy, bypass it at the

REF pin with a 4.7µF capacitor.

Analog Input

The MAX1132/MAX1133 use a capacitive DAC that

provides an inherent track/hold function. Drive AIN with

a source impedance less than 10Ω. Any signal condi-

tioning circuitry must settle with 16-bit accuracy in less

than 500ns. Limit the input bandwidth to less than half

the sampling frequency to eliminate aliasing. The

MAX1132/MAX1133 has a complex input impedance

which varies from unipolar to bipolar mode (Figure 1).

Input Range

The analog input range in unipolar mode is 0 to +12V

for the MAX1132, and 0 to +4.096V for the MAX1133. In

bipolar mode, the analog input can be -12V to +12V for

the MAX1132, and -4.096V to +4.096V for the

MAX1133. Unipolar and bipolar mode is programmed

with the UNI/BIP bit of the Control Byte. When using a

reference other than the MAX1132/MAX1133’s internal

+4.096V reference, the full-scale input range will vary

accordingly. The full-scale input range depends on the

voltage at REF and the sampling mode selected (Tables

3 and 4).

Input Acquisition and Settling

Clocking in a Control Byte starts input acquisition. In

bipolar mode the main capacitor array starts acquiring

the input as soon as a start bit is recognized. If unipolar

mode is selected by the second DIN bit, the part will

immediately switch to unipolar sampling mode and

acquire a sample.

Acquisition can be extended by eight clock cycles by

setting M1 = 1, M0 = 1 (long acquisition mode). The

sampling instant in short acquisition completes on the

falling edge of the sixth clock cycle after the start bit

(Figure 2).

Acquisition is 5.5 clock cycles in short acquisition

mode and 13.5 clock cycles in long acquisition mode.

Short acquisition mode is 24 clock cycles per conver-

sion. Using the external clock to run the conversion

process limits unipolar conversion speed to 125ksps

instead of 200ksps in bipolar mode. The input resis-

tance in unipolar mode is larger than that of bipolar

mode (Figure1). The RC time constant in unipolar mode

is larger than that of bipolar mode, reducing the maxi-

mum conversion rate in 24 external clock mode. Long

acquisition mode with external clock allows both unipo-

lar and bipolar sampling of 150ksps (4.8MHz/32 clock

cycles) by adding eight extra clock cycles to the con-

version.

MAX1132/MAX1133

16-Bit ADC, 200ksps, 5V Single-Supply

with Reference

______________________________________________________________________________________ 13

+5V

510kΩ

100kΩ

24kΩ

0.22µF

REFADJ

MAX1132

Figure 7. MAX1132 Reference-Adjust Circuit

MAX1132/MAX1133

Most applications require an input buffer amplifier. If

the input signal is multiplexed, the input channel should

be switched immediately after acquistion, rather than

near the end of or after a conversion. This allows more

time for the input buffer amplifier to respond to a large

step-change in input signal. The input amplifier must

have a high enough slew-rate to complete the required

output voltage change before the beginning of the

acquisition time. At the beginning of acquisition, the

capacitive DAC is connected to the amplifier output,

causing some output disturbance. Ensure that the sam-

pled voltage has settled to within the required limits

before the end of the acquisition time. If the frequency

of interest is low, AIN can be bypassed with a large

enough capacitor to charge the capacitive DAC with

very little change in voltage. However, for AC use, AIN

must be driven by a wideband buffer (at least 10MHz),

which must be stable with the DACs capacitive load (in

parallel with any AIN bypass capacitor used) and also

settle quickly (Figures 8 or 9).

Digital Noise

Digital noise can couple to AIN and REF. The conver-

sion clock (SCLK) and other digital signals that are

active during input acquisition contribute noise to the

conversion result. If the noise signal is synchronous to

the sampling interval, an effective input offset is pro-

duced. Asynchronous signals produce random noise

on the input, whose high-frequency components may

be aliased into the frequency band of interest. Minimize

noise by presenting a low impedance (at the frequen-

cies contained in the noise signal) at the inputs. This

requires bypassing AIN to AGND, or buffering the input

with an amplifier that has a small-signal bandwidth of

several MHz, or preferably both. AIN has a bandwidth

of about 4MHz.

Offsets resulting from synchronous noise (such as the

conversion clock) are canceled by the MAX1132/

MAX1133’s calibration scheme. The magnitude of the

offset produced by a synchronous signal depends on

the signal’s shape. Recalibration may be appropriate if

the shape or relative timing of the clock or other digital

signals change, as might occur if more than one clock

signal or frequency is used.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the MAX1132/

MAX1133’s THD (-90dB) at frequencies of interest. If

the chosen amplifier has insufficient common-mode

rejection, which results in degraded THD performance,

use the inverting configuration to eliminate errors from

common-mode voltage. Low temperature-coefficient

resistors reduce linearity errors caused by resistance

changes due to self-heating. To reduce linearity errors

due to finite amplifier gain, use an amplifier circuit with

sufficient loop gain at the frequencies of interest.

DC Accuracy

If DC accuracy is important, choose a buffer with an

offset much less than the MAX1132/MAX1133’s maxi-

mum offset (±6mV), or whose offset can be trimmed

while maintaining good stability over the required tem-

perature range.

16-Bit ADC, 200ksps, 5V Single-Supply

with Reference

14 ______________________________________________________________________________________

Table 3. Unipolar Full Scale and Zero Scale

PART REFERENCE ZERO SCALE FULL SCALE

Internal 0 +12V

MAX1132

External 0 +12(V

REF

/4.096)

Internal 0 +4.096V

MAX1133

External 0 +V

REF

Table 4. Bipolar Full Scale, Zero Scale, and Negative Scale

PART REFERENCE

NEGATIVE FULL

SCALE

ZERO SCALE FULL SCALE

Internal -12V 0 +12V

MAX1132

External -12(V

REF

/4.096) 0 +12(V

REF

/4.096)

Internal -4.096V 0 +4.096V

MAX1133

External -V

REF

0+V

REF

Operating Modes and Serial Interfaces

The MAX1132/MAX1133 are fully compatible with

MICROWIRE and SPI/QSPI devices. MICROWIRE and

SPI/QSPI both transmit a byte and receive a byte at the

same time. The simplest software interface requires

only three 8-bit transfers to perform a conversion (one

8-bit transfer to configure the ADC, and two more 8-bit

transfers to clock out the 16-bit conversion result).

Short Acquisition Mode (24 SCLK)

Configure short acquisition by setting M1 = 0 and M0 =

0. In short acquisition mode, the acquisition time is 5.5

clock cycles. The total period is 24 clock cycles per

conversion.

Mode 2 Long Acquisition Mode (32 SCLK)

Configure long acquisition by setting M1 = 1 and M0 =

1. In long acquisition mode, the acquisition time is 13.5

clock cycles. The total period is 32 clock cycles per

conversion.

Calibration Mode

A calibration is initiated through the serial interface by

setting M1 = 0, M0 = 1. Calibration can be done in

either internal or external clock mode, though it is desir-

able that the part be calibrated in the same mode in

which it will be used to do conversions. The part will

remain in calibration mode for approximately 80,000

clock cycles unless the calibration is aborted.

Calibration is halted if RST or SHDN goes low, or if a

valid start condition occurs.

Software Shutdown

A software power-down is initiated by setting M1 = 1,

M0 = 0. After the conversion completes, the part shuts

down. It reawakens upon receiving a new start bit.

Conversions initiated with M1 = 1 and M0 = 0 (shut-

down) use the acquisition mode selected for the previ-

ous conversion.

Shutdown Mode

The MAX1132/MAX1133 may be shut down by pulling

SHDN low or by asserting software shutdown. In addi-

tion to lowering power dissipation to 13µW, consider-

able power can be saved by shutting down the

converter for short periods (duration will be affected by

REF startup time with internal reference) between con-

versions. There is no need to perform a calibration after

the converter has been shut down, unless the time in

MAX1132/MAX1133

16-Bit ADC, 200ksps, 5V Single-Supply

with Reference

______________________________________________________________________________________ 15

+15V

-15V

0.0033

0.1

100pF

Ω

AIN

MAX427

ELANTEC

EL2003

Figure 8. AIN Buffer for AC/DC Use

+5V

-5V

AIN

0.1

Ω

510

Ω

MAX410

Figure 9. ±5V Buffer for AC/DC Use Has ±3.5V Swing

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MAX1132BCAP+

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Analog to Digital Converters - ADC 16-Bit 200ksps 5V Single-Supply w/Ref

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MAX1132BCAP+

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