RT9030A
7
DS9030A-02 December 2013 www.richtek.com
©
Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Applications Information
Capacitor Selection
In order to confirm the regulator stability and performance,
X7R/X5R or other better quality ceramic capacitor should
be selected.
Like any low-dropout regulator, the external capacitors used
with the RT9030A must be carefully selected for regulator
stability and performance. Use at least 1μF of capacitor
on the RT9030A's input and the amount of capacitance
can be increased without limit. The input capacitor should
be located in less than 0.5 inch from the input pin of the
IC and returned to a clean analog ground. The capacitor
with larger value and lower ESR (equivalent series
resistance) provides better PSRR and line-transient
response.
The output capacitor must meet both requirements for
minimum amount of capacitance in all LDOs application.
The RT9030A is designed specifically to work with low
ESR ceramic output capacitor in space-saving and
performance consideration. Using a ceramic capacitor
whose value is at least 1μF on the RT9030A output ensures
stability. Output capacitor with larger capacitance can
reduce noise and improve load transient response, stability
and PSRR. The output capacitor should be located in less
than 0.5 inch from the VOUT pin of the RT9030A and
returned to a clean analog ground.
Enable
The RT9030A goes into shutdown mode when the EN pin
is in a logic low condition. During this condition, the pass
transistor, error amplifier and bandgap are turned off,
reducing the supply current to 0.7μA typical. The EN pin
can be directly tied to VIN to keep the part on.
Current limit
The RT9030A contains an independent current limiter,
which monitors and limits the output current to 600mA
(typ.) by controling the gate voltage of the pass transistor.
The output can be shorted to ground indefinitely without
damaging the part.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOT-23-5 packages, the thermal resistance, θ
JA
, is
250°C/W on a standard JEDEC 51-3 single-layer thermal
test board. The maximum power dissipation at T
A
= 25°C
can be calculated by the following formula :
P
D(MAX)
= (125°C − 25°C) / (250°C/W) = 0.400W for
SOT-23-5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 1. Derating Curve of Maximum Power Dissipation
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Single Layer PCB
