DS1267B
STACKED CONFIGURATION
The potentiometers of the DS1267B can be connected in series as shown in Figure 3. This is referred to
as the stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the S
OUT
pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S
OUT
output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, S
OUT
, will be that of the
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S
OUT
, will be that of the
potentiometer-1 wiper.
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1267B is the ability to control multiple devices from a single processor. Multiple
DS1267Bs can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267B a bit will appear at the C
OUT
output within a maximum delay of 50 nanoseconds.
The stack select bit of the DS1267B will always be the first out the part at the beginning of a transaction.
Additionally the C
OUT
pin is always active regardless of the state of
RST
. This allows one to read the I/O
shift register without changing its value.
CASCADING MULTIPLE DEVICES Figure 4
Maxim Integrated ............................................................................................................................................................................................. 4
DS1267B
The C
OUT
output of the DS1267B can be used to drive the DQ input of another DS1267B. When
connecting multiple devices, the total number of bits transmitted is always 17 times the number of
DS1267Bs in the daisy chain.
An optional feedback resistor can be placed between the C
OUT
terminal of the last device and the first
DS1267B DQ input, thus allowing the controlling processor to read as well as write data or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2 to 10k.
When reading data via the C
OUT
pin and isolation resistor, the DQ line is left floating by the reading
device. When
RST
is driven high, bit 17 is present on the C
OUT
pin, which is fed back to the input DQ
pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the
first position of the I/O shift register and bit 16 becomes present on C
OUT
and DQ of the next device. After
17 bits (or 17 times the number of DS1267Bs in the daisy chain), the data has shifted completely around
and back to its original position. When
RST
transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity, also known as integral nonlinearity, is defined as the difference between the actual
measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to
measure absolute linearity. Absolute linearity is given in terms of a minimum increment or expected
output when the wiper is moved one position. In the case of the test circuit, a minimum increment (MI) or
one LSB would equal 10/512 volts. The equation for absolute linearity is given as follows:
(1) ABSOLUTE LINEARITY (INL)
AL={V
O
(actual) - V
O
(expected)}/MI
Relative Linearity, also known as differential nonlinearity, is a measure of error between two adjacent
wiper position points and is given in terms of MI by equation (2).
(2) RELATIVE LINEARITY (DNL)
RL={V
O
(n+1) - V
O
(n)}/MI
Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267B at
25°C. The specification for absolute linearity of the DS1267B is ±0.75 MI typical. The specification for
relative linearity of the DS1267B is ±0.3 MI typical.
Maxim Integrated ............................................................................................................................................................................................. 5
DS1267B
LINEARITY MEASUREMENT CONFIGURATION Figure 5
NOTE:
In this setup, a ±2% delta in total resistance R0 to R1 would cause a ±2.5 MI error.
DS1267B ABSOLUTE AND RELATIVE LINEARITY Figure 6
TYPICAL APPLICATION CONFIGURATIONS
Figures 7 and 8 show two typical application configurations for the DS1267B. By connecting the wiper
terminal of the part to a high-impedance load, the effects of the wiper resistance is minimized, since the
wiper resistance can vary from 900 to 2000 depending on wiper voltage. Figure 7 presents the device
connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by the
following equation:
A
V
= -n/(255-n); where n = 0 to 255
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
LSB
Tap Position
Linearity vs. Tap Position
INL
DNL
DS1267B
10kΩ
Maxim Integrated ............................................................................................................................................................................................. 6

DS1267BS-050+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital Potentiometer ICs Dual 256-step digital potentiometer, 50k ohm end to end resistance
Lifecycle:
New from this manufacturer.
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