MAX2440/MAX2441/MAX2442
900MHz Image-Reject Receivers
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Detailed Description
The following sections describe each of the blocks
shown in the Functional Diagram.
Receiver
The MAX2440/MAX2441/MAX2442’s receive path con-
sists of a 900MHz low-noise amplifier, an image-reject
mixer, and an IF buffer amplifier.
The LNA’s gain and biasing are adjustable via the
LNAGAIN pin. Proper operation of this pin can provide
optimum performance over a wide range of signal lev-
els. The LNA can be placed in four modes by applying
a DC voltage on the LNAGAIN pin. See Table 1, as well
as the relevant Typical Operating Characteristics plots.
At low LNAGAIN voltages, the LNA is shut off, and the
input signal capacitively couples directly into the mixer
to provide maximum linearity for large-signal operation
(receiver close to transmitter). As the LNAGAIN voltage
is raised, the LNA begins to turn on. Between 0.5V and
1V at LNAGAIN, the LNA is partially biased and
behaves like a Class C amplifier. Avoid this operating
mode for applications where linearity is a concern. As
the LNAGAIN voltage reaches 1V, the LNA is fully
biased into Class A mode, and the gain is monotonical-
ly adjustable at LNAGAIN voltages above 1V. See the
Receiver Gain, Receiver IP3, and Receiver Noise
Figure vs. LNAGAIN plots in the Typical Operating
Characteristics for more information.
The downconverter is implemented using an image-
reject mixer consisting of an input buffer with two out-
puts, each of which is fed to a double-balanced mixer.
The local-oscillator (LO) port of each mixer is driven
from a quadrature LO. The LO is generated from an on-
chip oscillator and an external tank circuit. Its signal is
buffered and split into phase shifters, which provide
90° of phase shift across their outputs. This pair of LO
signals is fed to the mixers. The mixers’ outputs are
then passed through a second pair of phase shifters,
which provide a 90° phase shift across their outputs. The
resulting mixer outputs are then summed together. The
final phase relationship is such that the desired signal is
reinforced and the image signal is canceled. The down-
converter mixer output appears on the RXOUT pin, a
single-ended 330Ω output.
Phase Shifters
MAX2440/MAX2441/MAX2442 devices use passive
networks to provide quadrature phase shifting for the
receive IF and LO signals. Because these networks are
frequency selective, proper part selection is important.
Image rejection degrades as the IF and RF move away
from the designed optimum frequencies. Refer to the
Selector Guide on the front page of this data sheet.
Local Oscillator (LO)
The on-chip LO is formed by an emitter-coupled differ-
ential pair. An external LC resonant tank sets the oscil-
lation frequency. A varactor diode is typically used to
create a voltage-controlled oscillator (VCO). See the
Applications Information section and Figure 2 for an
example VCO tank circuit.
The LO may be overdriven in applications where an
external signal is available. The external LO signal
should be about 0dBm from 50Ω, and should be AC
coupled into either the TANK or TANK pin. Both TANK
and TANK require pull-up resistors to V
CC
. See the
Applications Information section and Figure 3 for
details.
The local oscillator resists LO pulling caused by changes
in load impedance that occur as the part is switched
from standby mode. The amount of LO pulling will be
affected if there is power at the RXIN port due to imper-
fect isolation in an external transmit/receive (T/R) switch.
Prescaler
The on-chip prescaler can be used in two different
modes: as a dual-modulus divide-by-64/65, or as oscil-
lator buffer amplifier. The DIV1 pin controls this func-
tion. When DIV1 is low, the prescaler is in dual-modulus
divide-by-64/65 mode; when it is high, the prescaler is
disabled and the oscillator buffer amplifier is enabled.
The buffer typically outputs -8dBm into a 50Ω load. To
minimize shutdown supply current, pull the DIV1 pin
low when in shutdown mode.
In divide-by-64/65 mode, the division ratio is controlled
by the MOD pin. When MOD is high, the prescaler is in
divide-by-64 mode; when it is low, it divides the LO fre-
quency by 65. The DIV1 pin must be at a logic low in
this mode.
LNA partially biased. Avoid this mode—
the LNA operates in a Class C manner
LNA capacitively bypassed, minimum
gain, maximum IP3
MODE
LNA at maximum gain (remains monotonic)
LNA gain is monotonically adjustable
1.5 < V ≤ V
CC
1.0 < V ≤ 1.5
0.5 < V < 1.0
0 < V ≤ 0.5
LNAGAIN
VOLTAGE (V)
Table 1. LNA Modes
