CAT25320
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7
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 12 significant address
bits are used by the CAT25320. The rest are don’t care bits,
as shown in Table 11. Internal programming will start after
the low to high CS
transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY
bit will indicate if the internal write
cycle is in progress (RDY
high), or the device is ready to
accept commands (RDY
low).
Page Write
After sending the first data byte to the CAT25320, the host
may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25320 is
automatically returned to the write disable state.
Table 11. BYTE ADDRESS
Device Address Significant Bits Address Don’t Care Bits # Address Clock Pulses
CAT25320 A11 − A0 A15 − A12 16
Figure 5. Byte WRITE Timing
SCK
SI
SO
0000 01 0
D7 D6 D5 D4 D3 D2 D1 D0
012345678
OPCODE
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
21 22 23 24 25 26 27 28 29 30 31
Dashed Line = mode (1, 1)
CS
A
0
A
N
0
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
SCK
SI
SO
0000 0 10
BYTE ADDRESS*
Data
Byte 1
012345678 212223
24−31
32−39
Data Byte N
OPCODE
7..1 0
24+(N−1)x8−1 .. 24+(N−1)x8
24+Nx8−1
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
A
N
A
0
Data
Byte 3
Data
Byte 2
0
* Please check the Byte Address Table (Table 11)
