74CBTLVD3861 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 14 December 2011 9 of 19
NXP Semiconductors
74CBTLVD3861
10-bit level-shifting bus switch with output enable
10. Dynamic characteristics
[1] All typical values are measured at T
amb
=25C and at nominal V
CC
.
[2] The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven
by an ideal voltage source (zero output impedance).
[3] t
pd
is the same as t
PLH
and t
PHL
.
[4] t
en
is the same as t
PZH
and t
PZL
.
[5] t
dis
is the same as t
PHZ
and t
PLZ
.
10.1 Waveforms
Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 16
Symbol Parameter Conditions T
amb
= 40 C to +85 C T
amb
= 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay An to Bn or Bn to An;
see Figure 14
[2][3]
V
CC
= 3.0 V to 3.6 V - - 0.11 - 0.22 ns
t
en
enable time OE to An or Bn;
see Figure 15
[4]
V
CC
= 3.0 V to 3.6 V 1.5 2.9 5.0 1.5 6.0 ns
t
dis
disable time OE to An or Bn;
see Figure 15
[5]
V
CC
= 3.0 V to 3.6 V 0.8 3.3 7.0 0.8 8.0 ns
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 14. The data input (An, Bn) to output (Bn, An) propagation delay times
001aai367
V
M
V
M
V
M
V
M
V
I
input
0 V
V
OH
output
V
OL
t
PHL
t
PLH
Table 9. Measurement points
Supply voltage Input Output
V
CC
V
M
V
I
t
r
= t
f
V
M
V
X
V
Y
3.0 V to 3.6 V 0.5V
CC
V
CC
2.0 ns 0.9 V V
OL
+0.15V V
OH
0.15 V
74CBTLVD3861 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 14 December 2011 10 of 19
NXP Semiconductors
74CBTLVD3861
10-bit level-shifting bus switch with output enable
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 15. Enable and disable times
001aan155
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
OL
V
OH
1.8 V
V
M
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
74CBTLVD3861 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 14 December 2011 11 of 19
NXP Semiconductors
74CBTLVD3861
10-bit level-shifting bus switch with output enable
Test data is given in Table 10.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 16. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 10. Test data
Supply voltage Load V
EXT
V
CC
C
L
R
L
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
3.0 V to 3.6 V 30 pF 1 k open GND 3.6 V

74CBTLVD3861PW,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Digital Bus Switch ICs 10-bit level-shift bus switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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