30 Copyright 2010 Cirrus Logic (All Rights Reserved) DS638F2
EP9315
Enhanced Universal Platform SOC Processor
PCMCIA Interface
PCMCIA Read Cycle
Note: MCWAITn asserted will extend the MCRD / IORD strobe time.
Parameter Symbol Min Typ Max Unit
AD setup to signal transition time
t
ADs
0--ns
DA setup to MCRDn / IORDn rising edge
t
s
10 - - ns
DA hold from MCRDn / IORDn rising edge
t
h
0--ns
MCDIR hold time
t
MCDh
0--ns
MCADENn/MCDAENn hold time
t
MCAh
0--ns
MCEHn/MCELn/MCREGn hold time
t
MCEh
0--ns
Wait Time
1
t
W
--
t
A
-[2 × t
HCLK
]
ns
Attribute Mode Timing
Attribute access time
t
A
[(AA + 1) × t
HCLK
] - 14 (AA + 1) × t
HCLK
-ns
Attribute hold time
t
H
[(HA + 1) × t
HCLK
] - 3 (HA + 1) × t
HCLK
-ns
Attribute space pre-charge delay time
t
p
(PA + 1) × t
HCLK
(PA + 1) × t
HCLK
-ns
Common Mode Timing
Common access time
t
A
[(AC + 1) × t
HCLK
] - 14 (AC + 1) × t
HCLK
-ns
Common hold time
t
H
[(HC + 1) × t
HCLK
] - 3 (HC + 1) × t
HCLK
-ns
Common space pre-charge delay time
t
p
(PC + 1) × t
HCLK
(PC + 1) × t
HCLK
-ns
I/O Mode Timing
I/O access time
t
A
[(AI + 1) × t
HCLK
] - 14 (AI + 1) × t
HCLK
-ns
I/O hold time
t
H
[(HI + 1) × t
HCLK
] - 3 (HI + 1) × t
HCLK
-ns
I/O space pre-charge delay time
t
p
(PI + 1) × t
HCLK
(PI + 1) × t
HCLK
-ns
Figure 17. PCMCIA Read Cycle Timing Measurement
MCADENn/
MCDAENn
MCEHn/
MCELn/
MCREGn
DA
(in)
MCDIR
MCRDn/
IORDn
t
MCDh
t
p
t
A
t
ADs
t
H
t
h
t
s
MCWAITn
AD
t
MCEh
t
MCAh
t
W
