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MAX9375EUA+

P1-P3P4-P6
MAX9375
Single LVDS/Anything-to-LVPECL Translator
4 _______________________________________________________________________________________
100
110
105
120
115
125
130
-40 10-15 35 60 85
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9375 toc04
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)
t
F
t
R
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, differential input voltage |V
ID
| = 0.2V, V
CM
= 1.2V, input frequency = 500MHz, outputs terminated with 50Ω ±1% to
V
CC
- 2.0V, T
A
= +25°C, unless otherwise noted.)
Detailed Description
The MAX9375 is a fully differential, high-speed, any-
thing-to-LVPECL translator designed for signal rates up
to 2GHz. The MAX9375’s extremely low propagation
delay and high speed make it ideal for various high-
speed network routing and backplane applications.
The MAX9375 accepts any differential input signals
within the supply rails and with a minimum amplitude of
100mV. Inputs are fully compatible with the LVDS,
LVPECL, HSTL, and CML differential signaling stan-
dards. Outputs are LVPECL and have sufficient current
to drive 50Ω transmission lines.
Inputs
Inputs have a wide common-mode range of 0.05V to
(V
CC
- 0.05V), which accommodates any differential
signals within rails, and requires a minimum of 100mV
to switch the outputs. This allows the MAX9375 inputs
to support virtually any differential signaling standard.
LVPECL Outputs
The MAX9375 outputs are emitter followers that require
external resistive paths to a voltage source (V
T
= V
CC
- 2.0V typ) more negative than worst-case V
OL
for proper
static and dynamic operation. When properly terminat-
ed, the outputs generate steady-state voltage levels,
V
OL
or V
OH
with fast transition edges between state
levels. Output current always flows into the termination
during proper operation.
Pin Description
PIN NAME FUNCTION
1, 8 V
CC
Positive Supply. Bypass from V
CC
to
GND with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as
close to the device as possible with the
smaller value capacitor closest to the
device.
2 IN LVDS/Anything Noninverting Input
3 IN LVDS/Anything Inverting Input
4, 5 GND Power Supply Ground Connection
6 OUT
Differential LVPECL Inverting Output.
Terminate with 50Ω ±1% to V
CC
- 2V.
7 OUT
Differential LVPECL Noninverting Output.
Terminate with 50Ω ±1% to V
CC
- 2V.
390
410
400
430
420
440
450
-40 10-15 35 60 85
PROPAGATION DELAY
vs. TEMPERATURE
MAX9375 toc03
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
t
PLH
t
PHL
Applications Information
Output Termination
Terminate the outputs with 50Ω to (V
CC
- 2V) or use
equivalent Thevenin terminations. Terminate OUT and
OUT with identical termination on each for low-output
distortion. When a single-ended signal is taken from the
differential output, terminate both OUT and OUT. Ensure
that output currents do not exceed the current limits as
specified in the Absolute Maximum Ratings. Under all
operating conditions, the device’s total thermal limits
should be observed.
Supply Bypassing
Bypass V
CC
to ground with high-frequency surface-
mount ceramic 0.1µF and 0.01µF capacitors. Place the
capacitors as close to the device as possible with the
0.01µF capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
MAX9375
Single LVDS/Anything-to-LVPECL Translator
_______________________________________________________________________________________ 5
V
CM
(MAX) = V
CC
- 0.05V
V
CC
GND
V
ID
V
CM
(MIN) = 0.05V
V
ID
Figure 1. Input Definitions
Chip Information
TRANSISTOR COUNT: 614
PROCESS: Bipolar
80%
OUT - OUT
20%
20%
80%
0V DIFFERENTIAL
t
F
t
R
V
ID
0V DIFFERENTIAL
t
PLH
t
PHL
V
OH
V
OL
V
OH -
V
OL
V
OH -
V
OL
V
OH -
V
OL
DIFFERENTIAL OUTPUT
WAVEFORM
IN
OUT
IN
OUT
Figure 2. Differential Input-to-Output Propagation Delay Timing
Diagram
MAX9375
Single LVDS/Anything-to-LVPECL Translator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
PACKAGE OUTLINE, 8L uMAX/uSOP
1
1
21-0036
J
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
MAX
0.043
0.006
0.014
0.120
0.120
0.198
0.026
0.007
0.037
0.0207 BSC
0.0256 BSC
A2
A1
c
e
b
A
L
FRONT VIEW
SIDE VIEW
E H
0.6±0.1
0.6±0.1
ÿ 0.50±0.1
1
TOP VIEW
D
8
A2
0.030
BOTTOM VIEW
1
6∞
S
b
L
H
E
D
e
c
0∞
0.010
0.116
0.116
0.188
0.016
0.005
8
4X S
INCHES
-
A1
A
MIN
0.002
0.950.75
0.5250 BSC
0.25 0.36
2.95 3.05
2.95 3.05
4.78
0.41
0.65 BSC
5.03
0.66
6∞0∞
0.13 0.18
MAX
MIN
MILLIMETERS
- 1.10
0.05 0.15
α
α
DIM
P1-P3P4-P6

MAX9375EUA+

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Buy MAX9375EUA+
Manufacturer:
Maxim Integrated
Description:
Translation - Voltage Levels Single LVDS/Anything To-LVPECL Translator
Lifecycle:
New from this manufacturer.
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