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MT4HTF6464AZ-667H1

P1-P3P4-P6P7-P9P10-P12P13-P15
Table 12: DDR2 I
DD
Specifications and Conditions – 2GB (Die Rev C) (Continued)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 Units
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus inputs
are
I
DD3N
TBD TBD mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD4W
TBD TBD mA
Operating burst read current: All device banks open; Continuous burst
read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
I
DD4R
TBD TBD mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC
(I
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD5
TBD TBD mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
TBD TBD mA
Operating bank interleave read current: All device banks interleaving
reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH,
S# is HIGH between valid commands; Address bus inputs are stable during
deselects; Data bus inputs are switching
I
DD7
TBD TBD mA
512MB, 1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM UDIMM
I
DD
Specifications
PDF: 09005aef83b961d6
htf9c64_128_256x72az – Rev. C 12/10 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 13: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
1.7 3.6 V
Input high voltage: logic 1; All inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: logic 0; All inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
–
0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 14: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time bus must be free before a new transition can start
t
BUF 1.3
–
µs
Data-out hold time
t
DH 200
–
ns
SDA and SCL fall time
t
F
–
300 ns 2
SDA and SCL rise time
t
R
–
300 ns 2
Data-in hold time
t
HD:DAT 0
–
µs
Start condition hold time
t
HD:STA 0.6
–
µs
Clock HIGH period
t
HIGH 0.6
–
µs
Noise suppression time constant at SCL, SDA inputs
t
I
–
50 ns
Clock LOW period
t
LOW 1.3
–
µs
SCL clock frequency
t
SCL
–
400 kHz
Data-in setup time
t
SU:DAT 100
–
ns
Start condition setup time
t
SU:STA 0.6
–
µs 3
Stop condition setup time
t
SU:STO 0.6
–
µs
WRITE cycle time
t
WRC
–
10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
512MB, 1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
PDF: 09005aef83b961d6
htf9c64_128_256x72az – Rev. C 12/10 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 240-Pin DDR2 UDIMM
30.5 (1.2)
29.85 (1.175)
Pin 1
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.3 (0.091) TYP
5.0 (0.197) TYP
123.0 (4.84)
TYP
1.0 (0.039)
TYP
0.8 (0.031)
TYP
2.0 (0.079) R
(4X)
0.76 (0.03) R
Pin 120
Front view
133.5 (5.256)
133.2 (5.244)
63.0 (2.48)
TYP
55.0 (2.165)
TYP
10.0 (0.394)
TYP
Back view
Pin 240
Pin 121
1.37 (0.054)
1.17 (0.046)
2.70 (0.106)
MAX
2.2 (0.087) TYP
1.0 (0.039) TYP
3.05 (0.12) TYP
70.68 (2.78)
TYP
U1 U2 U3 U4 U5 U6 U7 U8 U9
U10
45° (4X)
No components this side of module
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
additional design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
512MB, 1GB, 2GB (x72, SR) 240-Pin DDR2 SDRAM UDIMM
Module Dimensions
PDF: 09005aef83b961d6
htf9c64_128_256x72az – Rev. C 12/10 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15

MT4HTF6464AZ-667H1

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Manufacturer:
Micron
Description:
DRAM Module DDR2 SDRAM 512Mbyte 240UDIMM
Lifecycle:
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