LTC3588-2
7
35882fc
For more information www.linear.com/LTC3588-2
PIN FUNCTIONS
PZ1 (Pin 1): Input connection for piezoelectric element or
other AC source (used in conjunction with PZ2).
PZ2 (Pin 2): Input connection for piezoelectric element or
other AC source (used in conjunction with PZ1).
CAP (Pin 3): Internal rail referenced to V
IN
to serve as gate
drive for buck PMOS switch. A F capacitor should be
connected between CAP and V
IN
. This pin is not intended
for use as an external system rail.
V
IN
(Pin 4): Rectified Input Voltage. A capacitor on this
pin serves as an energy reservoir and input supply for the
buck regulator. The V
IN
voltage is internally clamped to a
maximum of 20V (typical).
SW (Pin 5): Switch Pin for the Buck Switching Regulator.
A 22µH or larger inductor should be connected from SW
to V
OUT
.
V
OUT
(Pin 6): Sense pin used to monitor the output volt-
age and adjust it through internal feedback.
V
IN2
(Pin 7): Internal low voltage rail to serve as gate drive
for buck NMOS switch. Also serves as a logic high rail for
output voltage select bits D0 and D1. A 4.7µF capacitor
should be connected from V
IN2
to GND. This pin is not
intended for use as an external system rail.
D1 (Pin 8): Output Voltage Select Bit. D1 should be tied
high to V
IN2
or low to GND to select desired V
OUT
(see
Table 1).
D
0 (Pin 9): Output Voltage Select Bit. D0 should be tied
high to V
IN2
or low to GND to select desired V
OUT
(see
Table 1).
PGOOD (Pin 10): Power good output is logic high when
V
OUT
is above 92% of the target value. The logic high is
referenced to the V
OUT
rail.
GND (Exposed Pad Pin 11): Ground. The Exposed Pad
should be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3588-2.
BLOCK DIAGRAM
35882 BD
D1, D0
PZ2
PZ1
V
IN
UVLO
BUCK
CONTROL
INTERNAL RAIL
GENERATION
2
BANDGAP
REFERENCE
SLEEP
PGOOD
COMPARATOR
CAP
SW
GND
PGOOD
V
IN2
V
OUT
20V
5
3
7
11
10
6
8, 9
2
1
4
LTC3588-2
8
35882fc
For more information www.linear.com/LTC3588-2
The LTC3588-2 is an ultralow quiescent current power
supply designed specifically for energy harvesting and/or
low current step-down applications. The part is designed to
interface directly to a piezoelectric or alternative A/C power
source, rectify a voltage waveform and store harvested
energy on an external capacitor, bleed off any excess power
via an internal shunt regulator, and maintain a regulated
output voltage by means of a nanopower high efficiency
synchronous buck regulator.
Internal Bridge Rectifier
The LTC3588-2 has an internal full-wave bridge rectifier
accessible via the differential PZ1 and PZ2 inputs that
rectifies AC inputs such as those from a piezoelectric
element. The rectified output is stored on a capacitor at
the V
IN
pin and can be used as an energy reservoir for the
buck converter. The low-loss bridge rectifier has a total
drop of about 400mV with typical piezo generated currents
(~10µA). The bridge is capable of carrying up to 50mA.
One side of the bridge can be operated as a single-ended
DC input. PZ1 and PZ2 should never be shorted together
when the bridge is in use.
Undervoltage Lockout (UVLO)
When the voltage on V
IN
rises above the UVLO rising
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output capacitor.
A wide (~2V) UVLO hysteresis window allows a portion of
the energy stored on the input capacitor to be transferred
to the output capacitor by the buck. When the input capaci-
tor voltage is depleted below the UVLO falling threshold
the buck converter is disabled. Extremely low quiescent
current (830nA typical, V
IN
= 12V) in UVLO allows energy
to accumulate on the input capacitor in situations where
energy must be harvested from low power sources.
Internal Rail Generation
Two internal rails, CAP and V
IN2
, are generated from V
IN
and
are used to drive the high side PMOS and low side NMOS
of the buck converter, respectively. Additionally the V
IN2
rail serves as logic high for output voltage select bits D
0
and D1. The V
IN2
rail is regulated at 4.8V above GND while
the CAP rail is regulated at 4.8V below V
IN
. These are not
intended to be used as external rails. Bypass capacitors
are connected to the CAP and V
IN2
pins to serve as energy
reservoirs for driving the buck switches. When V
IN
is below
4.8V, V
IN2
is equal to V
IN
and CAP is held at GND. Figure 1
shows the ideal V
IN
, V
IN2
and CAP relationship.
Figure 1. Ideal V
IN
, V
IN2
and CAP Relationship
OPERATION
Buck Operation
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
V
OUT
sense pin. The buck converter charges an output
capacitor through an inductor to a value slightly higher
than the regulation point. It does this by ramping the
inductor current up to 260mA through an internal PMOS
switch and then ramping it down to 0mA through an
internal NMOS switch. This efficiently delivers energy
to the output capacitor. The ramp rate is determined by
V
IN
, V
OUT
, and the inductor value. If the input voltage
falls below the UVLO falling threshold before the output
voltage reaches regulation, the buck converter will shut
off and will not be turned on until the input voltage again
rises above the UVLO rising threshold. During this time
the output voltage will be loaded by approximately 100nA.
When the buck brings the output voltage into regulation
the converter enters a low quiescent current sleep state
that monitors the output voltage with a sleep comparator.
During this operating mode load current is provided by
the buck output capacitor. When the output voltage falls
below the regulation point the buck regulator wakes up
and the cycle repeats. This hysteretic method of providing
a regulated output reduces losses associated with FET
switching and maintains an output at light loads. The buck
delivers a minimum of 100mA of average current to the
output when it is switching
.
V
IN
(V)
0
VOLTAGE (V)
18
12
14
16
10
2
4
8
6
0
105
35882 F01
15
V
IN
V
IN2
CAP
LTC3588-2
9
35882fc
For more information www.linear.com/LTC3588-2
OPERATION
When the sleep comparator signals that the output has
reached the sleep threshold the buck converter may be
in the middle of a cycle with current still flowing through
the inductor. Normally both synchronous switches would
turn off and the current in the inductor would freewheel
to zero through the NMOS body diode. The LTC3588-2
keeps the NMOS switch on during this time to prevent the
conduction loss that would occur in the diode if the NMOS
were off. If the PMOS is on when the sleep comparator
trips the NMOS will turn on immediately in order to ramp
down the current. If the NMOS is on it will be kept on until
the current reaches zero.
Though the quiescent current when the buck is switching
is much greater than the sleep quiescent current, it is still
a small percentage of the average inductor current which
results in high efficiency over most load conditions. The
buck operates only when sufficient energy has been ac-
cumulated in the input capacitor and the length of time the
converter needs to transfer energy to the output is much
less than the time it takes to accumulate energy. Thus, the
buck operating quiescent current is averaged over a long
period of time so that the total average quiescent current
is low. This feature accommodates sources that harvest
small amounts of ambient energy.
Four selectable voltages are available by tying the output
select bits, D0 and D1, to GND or V
IN2
. Table 1 shows the
four D0/D1 codes and their corresponding output voltages.
Table 1. Output Voltage Selection
D1 D0 V
OUT
V
OUT
QUIESCENT CURRENT (I
VOUT
)
0 0 3.45V 86nA
0 1 4.1V 101nA
1 0 4.5V 111nA
1 1 5.0V 125nA
The internal feedback network draws a small amount of
current from V
OUT
as listed in Table 1.
Power Good Comparator
A power good comparator produces a logic high referenced
to V
OUT
on the PGOOD pin the first time the converter
reaches the sleep threshold of the programmed V
OUT
,
signaling that the output is in regulation. The PGOOD pin
will remain high until V
OUT
falls to 92% of the desired
regulation voltage. Several sleep cycles may occur during
this time. Additionally, if PGOOD is high and V
IN
falls below
the UVLO falling threshold, PGOOD will remain high until
V
OUT
falls to 92% of the desired regulation point. This
allows output energy to be used even if the input is lost.
Figure 2 shows the behavior for V
OUT
= 5V and a 10µA
load. At t = 2s V
IN
becomes high impedance and is dis-
charged by the quiescent current of the LTC3588-2 and
through servicing V
OUT
which is discharged by its own
leakage current. V
IN
crosses UVLO falling but PGOOD
remains high until V
OUT
decreases to 92% of the desired
regulation point. The PGOOD pin is designed to drive a
microprocessor or other chip I/O and is not intended to
drive higher current loads such as an LED.
The D0/D1 inputs can be switched while in regulation as
shown in Figure 3. If V
OUT
is programmed to a voltage with
a PGOOD falling threshold above the old V
OUT
, PGOOD will
TIME (sec)
0
VOLTAGE (V)
20
14
16
18
12
4
6
8
2
10
0
108
35882 F02
1242 6
C
IN
= 10µF,
C
OUT
= 47µF,
I
LOAD
= 10µA
V
IN
= UVLO FALLING
V
OUT
V
IN
PGOOD
Figure 2. PGOOD Operation During Transition to UVLO
Figure 3. PGOOD Operation During D0/D1 Transition
TIME (ms)
0
V
OUT
VOLTAGE (V)
6
5
4
3
2
1
0
181614
12108642
35882 F03
20
C
OUT
= 100µF, I
LOAD
= 100mA
V
OUT
PGOOD = LOGIC 1
D1=D0=0
D1=D0=1
D1=D0=0

LTC3588IMSE-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Power Management Specialized - PMIC Piezoelectric Energy Harvesting Power Supply
Lifecycle:
New from this manufacturer.
Delivery:
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