PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
9 ©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Electrical Specifications
Table 9: IDD Specifications and Conditions – 256MB
Values shown for DDR2 SDRAM components only
Parameter/Condition Symbol -667 -53E -40E Units
Operating one bank active-precharge current;
t
CK =
t
CK (IDD),
t
RC =
t
RC
(IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD0 810 720 675 mA
Operating one bank active-read-precharge current; I
OUT = 0mA; BL = 4, CL =
CL (I
DD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data pattern is same as IDD4W
I
DD1 900 810 765 mA
Precharge power-down current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
I
DD2P 45 45 45 mA
Precharge quiet standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are floating
IDD2Q 360 315 225 mA
Precharge standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is HIGH,
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
IDD2N 360 315 270 mA
Active power-down current; All device banks open;
t
CK =
t
CK
(I
DD); CKE is LOW; Other control and address bus inputs are
stable; Data bus inputs are floating
Fast PDN Exit
MR[12] = 0
I
DD3P 270 225 180 mA
Slow PDN Exit
MR[12] = 1
54 54 54 mA
Active standby current; All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
IDD3N 450 360 270 mA
Operating burst write current; All device banks open, continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
DD4W 1,710 1,440 1,125 mA
Operating burst read current; All device banks open, continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD4R 1,620 1,350 1,035 mA
Burst refresh current;
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
DD5 1,620 1,530 1,485 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are floating
I
DD6454545mA
Operating bank interleave read current; All device banks interleaving reads,
IOUT= 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) -1 ×
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC
=
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching; See I
DD7 Conditions for detail
I
DD7 2250 2,160 2,070 mA