MT9HTF12872KY-53ED1 Datasheet MT9HTF12872KY-40EA1, MT9HTF12872KY-40ED1, MT9HTF12872KY-53EA1 | P7-P9

PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF9C32_64_128x72K.fm - Rev. C 9/06 EN

256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM

General Description

The MT9HTF3272(P)K, MT9HTF6472(P)K, and MT9HTF12872(P)K DDR2 SDRAM

modules are high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB

memory modules organized in x72 configuration. DDR2 SDRAM modules use internally

configured quad-bank (256Mb, 512Mb) or eight-bank (1Gb) DDR2 SDRAM devices.

DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-

wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding

n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

PLL and Register Operation

DDR2 SDRAM modules operate in registered mode, where the command/address input

signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM

devices on the following rising clock edge (data access is delayed by one clock cycle). A

phase-lock loop (PLL) on the module receives and redrives the differential clock signals

(CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and

clock loading. Registered mode will add one clock cycle to CL.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256

bytes. The first 128 bytes can be programmed by Micron to identify the module type and

various SDRAM organizations and timing parameters. The remaining 128 bytes of

storage are available for use by the customer. System READ/WRITE operations between

the master (system logic) and the slave EEPROM device occur via a standard I

C bus

using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which

provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on

the module, permanently disabling hardware write protect.

PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF9C32_64_128x72K.fm - Rev. C 9/06 EN

256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM

Electrical Specifications

Stresses greater than those listed in Table 8 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

Capacitance

At DDR2 data rates, Micron encourages designers to simulate the performance of the

module to achieve optimum values. When inductance and delay parameters associated

with trace lengths are used in simulations, they are significantly more accurate and real-

istic than a gross estimation of module capacitance. Simulations can then render a

considerably more accurate result. JEDEC modules are now designed by using simula-

tions to close timing budgets.

Table 8: Absolute Maximum DC Ratings

Symbol Parameter Min Max Units

VDD supply voltage relative to VSS

–1.0 +2.3 V

DDQ

VDDQ supply voltage relative to VSS

–0.5 +2.3 V

DDL

VDDL supply voltage relative to Vss

–0.5 +2.3 V

IN, VOUT

Voltage on any pin relative to VSS

–0.5 +2.3 V

STG

Storage temperature

–55 +100 °C

CASE

DDR2 SDRAM device operating temperature

0+85°C

OPR

Operating temperature

0+55°C

Input leakage current; Any input 0V ≤ VIN ≤ VDD;

REF input 0V ≤ VIN ≤0.95V; (All other pins not

under test = 0V)

Command/Address,

RAS#, CAS#, WE# S#,

CKE, ODT, DM

–5 +5 µA

CK, CK#

–10 +10

Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs

and ODT are disabled

DQ, DQS, DQS#

–5 +5 µA

VREF

VREF leakage current; VREF = Valid VREF level

–18 +18 µA

PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF9C32_64_128x72K.fm - Rev. C 9/06 EN

256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM

Electrical Specifications

Table 9: IDD Specifications and Conditions – 256MB

Values shown for DDR2 SDRAM components only

Parameter/Condition Symbol -667 -53E -40E Units

Operating one bank active-precharge current;

CK =

CK (IDD),

RC =

(IDD),

RAS =

RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

DD0 810 720 675 mA

Operating one bank active-read-precharge current; I

OUT = 0mA; BL = 4, CL =

CL (I

DD), AL = 0;

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN (IDD),

RCD =

RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data pattern is same as IDD4W

DD1 900 810 765 mA

Precharge power-down current; All device banks idle;

CK =

CK (IDD); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are

floating

DD2P 45 45 45 mA

Precharge quiet standby current; All device banks idle;

CK =

CK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus

inputs are floating

IDD2Q 360 315 225 mA

Precharge standby current; All device banks idle;

CK =

CK (IDD); CKE is HIGH,

S# is HIGH; Other control and address bus inputs are switching; Data bus inputs

are switching

IDD2N 360 315 270 mA

Active power-down current; All device banks open;

CK =

DD); CKE is LOW; Other control and address bus inputs are

stable; Data bus inputs are floating

Fast PDN Exit

MR[12] = 0

DD3P 270 225 180 mA

Slow PDN Exit

MR[12] = 1

54 54 54 mA

Active standby current; All device banks open;

CK =

CK (IDD),

RAS =

RAS

MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

IDD3N 450 360 270 mA

Operating burst write current; All device banks open, continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

DD4W 1,710 1,440 1,125 mA

Operating burst read current; All device banks open, continuous burst reads,

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

DD4R 1,620 1,350 1,035 mA

Burst refresh current;

CK =

CK (IDD); REFRESH command at every

RFC (IDD)

interval; CKE is HIGH, S# is HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs are switching

DD5 1,620 1,530 1,485 mA

Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address

bus inputs are FLOATING; Data bus inputs are floating

DD6454545mA

Operating bank interleave read current; All device banks interleaving reads,

IOUT= 0mA; BL = 4, CL = CL (IDD), AL =

RCD (IDD) -1 ×

CK (IDD);

CK =

CK (IDD),

RC (IDD),

RRD =

RRD (IDD),

RCD =

RCD (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are stable during deselects; Data bus inputs

are switching; See I

DD7 Conditions for detail

DD7 2250 2,160 2,070 mA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MT9HTF12872KY-53ED1

Mfr. #:

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Manufacturer:

Micron

Description:

MODULE DDR2 SDRAM 1GB 244MRDIMM

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