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NBSG53AMNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 15
1 Publication Order Number:
NBSG53A/D
NBSG53A
2.5 V/3.3 V SiGe Selectable
Differential Clock and Data
D Flip-Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi-function differential D flip-flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaCommt family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16-pin
Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS*, reset, and select
inputs. Differential inputs incorporate internal 50 W termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak-to-peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single-ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Features
• Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 3, 5, 7, 9, and 10)
• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 4, 6, 8, 9, and 10)
• 210 ps Typical Propagation Delay (OLS = FLOAT)
• 45 ps Typical Rise and Fall Times (OLS = FLOAT)
• DIV/2 Mode (Active with Select Low)
• DFF Mode (Active with Select High)
• Selectable Swing PECL Output with Operating Range: V
CC
= 2.375 V
to 3.465 V with V
EE
= 0 V
• Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
• Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak-to-Peak Output)
• 50 W Internal Input Termination Resistors on all Differential Inputs
• These are Pb-Free Devices
*Output Level Select
MARKING DIAGRAM*
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN−16
MN SUFFIX
CASE 485G
16
SG
53A
ALYWG
G
1
(Note: Microdot may be in either location)
1
NBSG53A
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2
VTD D D VTD
V
CC
R SEL OLS
V
EE
Q
Q
V
CC
VTCLK
CLK
CLK
VTCLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NBSG53A
Exposed Pad
(EP)
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTCLK −
Internal 50 W Termination Pin. See Table 4.
2 CLK ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
3 CLK ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
4 VTCLK −
Internal 50 W Termination Pin. See Table 4.
5 VTD −
Internal 50 W termination pin. See Table 4.
6 D ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
7 D ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
8 VTD −
Internal 50 W Termination Pin. See Table 4.
9,16 V
CC
− Positive Supply Voltage
10 Q RSECL Output
NonInverted Differential Output. Typically Terminated with 50 W Resistor to
V
TT
= V
CC
− 2 V.
11 Q RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to
V
TT
= V
CC
− 2 V.
12 V
EE
− Negative Supply Voltage
13 OLS* Input Input Pin for the Output Level Select (OLS). See Table 2.
14 SEL LVECL, LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 kW to V
EE
.
15 R LVECL, LVCMOS,
LVTTL Input
Reset D Flip-Flop. Internal 75 kW to V
EE
.
− EP The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat-sinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to V
EE
on the PC board.
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD
, VTCLK, VTCLK) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self-oscillation.
3. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2 kW resistor should be connected from OLS pin to V
EE
.
NBSG53A
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3
Figure 2. Simplified Logic Diagram
D
D
SEL
CLK
CLK
VTD
V
CC
Q
Q
Flip−Flop
(DIV/2)
Flip−Flop
(DFF)
R
D
D
VTD
OLS
R
Q
Q
V
EE
VTCLK
VTCLK
R
75 kW75 kW
50 W
50 W
50 W
50 W
0
1
2
2
2
2
2
2
2
Table 2. OUTPUT LEVEL SELECT (OLS)
OLS Q/Q VPP OLS Sensitivity
V
CC
800 mV OLS − 75 mV
V
CC
− 0.4 V 200 mV OLS $ 150 mV
V
CC
− 0.8 V 600 mV OLS $ 100 mV
V
CC
− 1.2 V 0 OLS $ 75 mV
V
EE
(Note 4) 400 mV OLS + 100 mV
Float 600 mV N/A
4. When an output level of 400 mV is desired and
V
CC
− V
EE
> 3.0 V, 2.0 kW resistor should be connected from
OLS to V
EE
.
Table 3. TRUTH TABLE
R SEL D CLK Q Function
H x x x L Reset
L H L Z L DFF
L H H Z H DFF
L L x Z Q DIV/2
Z = LOW to HIGH Transition
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS CONNECTIONS
CML Connect VTCLK, VTD and VTCLK, VTD to V
CC
LVDS Connect VTCLK, VTD and VTCLK, VTD Together
AC−COUPLED Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (V
IHCMR
)
RSECL, PECL, NECL Standard ECL Termination Techniques
LVTTL, LVCMOS An External Voltage (V
th
) should be Applied to the Unused Complementary Differential Input. Nominal V
th
is
1.5 V for LVTTL and V
CC
/2 for LVCMOS Inputs. This Voltage must be within the V
th
Specification.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NBSG53AMNG

Mfr. #:
Buy NBSG53AMNG
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2.5V/3.3V SiGe Diff Clock/Divider
Lifecycle:
New from this manufacturer.
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