Mixer
A unique feature of the MAX7032 is the integrated
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f
LO
= f
RF
- f
IF
). The image-rejection circuit
then combines these signals to achieve a typical 46dB
of image rejection over the full temperature range. Low-
side injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF out-
put is driven by a source follower, biased to create a
driving impedance of 330Ω to interface with an off-chip
330Ω ceramic IF filter. The voltage-conversion gain dri-
ving a 330Ω load is approximately 20dB. Note that the
MIXIN+ and MIXIN- inputs are functionally identical.
Integer-N Phase-Locked Loop (PLL)
The MAX7032 utilizes a fixed integer-N PLL to generate
the receive LO. All PLL components, including the loop fil-
ter, VCO, charge pump, asynchronous 24x divider, and
phase-frequency detector are integrated on-chip. The
loop bandwidth is approximately 500kHz. The relationship
between RF, IF, and reference frequencies is given by:
f
REF
= (f
RF
– f
IF
)/24
Intermediate Frequency (IF)
The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. The inter-
nal six AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass fil-
ter type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
For ASK data, the RSSI circuit demodulates the IF to
baseband by producing a DC output proportional to
the log of the IF signal level with a slope of approxi-
mately 15mV/dB. For FSK, the limiter output is fed into a
PLL to demodulate the IF. The FSK demodulation slope
is approximately 2.0mV/kHz.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and converts the fre-
quency deviation into a voltage difference. The PLL is
illustrated in Figure 1. The input to the PLL comes from
the output of the IF limiting amplifiers. The PLL control
voltage responds to changes in the frequency of the
input signal with a nominal gain of 2.0mV/kHz. For exam-
ple, an FSK peak-to-peak deviation of 50kHz generates
a 100mV
P-P
signal on the control line. This control volt-
age is then filtered and sliced by the baseband circuitry.
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
For more information on calibrating the FSK demodula-
tor, see the
Calibration
section. The maximum calibra-
tion time is 150µs. In discontinuous receive (DRX)
mode, the FSK demodulator calibration occurs auto-
matically just after the IC exits sleep mode, as long as
the ACAL bit is set to 1.
Data Filter
The data filter for the demodulated data is implemented
as a 2nd-order lowpass Sallen-Key filter. The pole loca-
tions are set by the combination of two on-chip resistors
and two external capacitors. Adjusting the value of the
external capacitors changes the corner frequency to
optimize for different data rates. The corner frequency in
kHz should be set to approximately 3 times the fastest
expected Manchester data rate in kbps from the trans-
mitter (1.5 times the fastest expected NRZ data rate) for
ASK. For FSK, the corner frequency should be set to
approximately 2 times the fastest expected Manchester
data rate in kbps from the transmitter (1 times the fastest
expected NRZ data rate). Keeping the corner frequency
near the data rate rejects any noise at higher frequen-
cies, resulting in an increase in receiver sensitivity.
Table 1 lists coefficients to calculate C
F1
and C
F2
.
