74HC_HCT4060_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 12 of 25
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] Qn+1 is the next Qn output.
[3] t
t
is the same as t
THL
and t
TLH
.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
12. Waveforms
C
PD
power
dissipation
capacitance
V
I
= GND to V
CC
1.5 V;
V
CC
=5V; f
i
=1MHz
[4]
-40- - - - -pF
Table 6. Dynamic characteristics
…continued
GND = 0 V; C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 7.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Waveforms showing the clock (RS) to output (Q3) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
001aai118
RS input
1/f
max
t
W
t
THL
t
TLH
t
PHL
t
PLH
V
OH
V
I
GND
V
OL
V
M
V
M
10 %
90 %90 %
10 %
Q3 output
