XRT71D03IVTR-F Datasheet XRT71D03IV-F, XRT71D03IVTR-F | P7-P9

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XRT71D03

3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

FL_2 O

FIFO Limit - channel 2:

See description pin 18

AGND ****

Analog Ground

AVDD ****

Analog Power Supply =5±5% or 3.3V±5%

GND ****

Digital Ground

RRCLK_2 O

Received Recovered Output (De-jittered) Clock - channel 2:

See description of pin 3

RRPOS_2 O

Received Recovered Positive Data (De-Jittered) Output - channel

See description of pin 4

RRNEG_2 O

Received Recovered Negative Data (De-Jittered) Output - channel

See description of pin 5

FSS I

FIFO Size Select Input:

When “High”: Selects 32 bits FIFO.

When “Low”: Selects 16 bits FIFO.

Internal 50 K Ohm pull-down resistor.

SDO O

Serial Data Output:

This pin will serially output the contents of the specified Command Register,

during “Read” Operations. The data, on this pin, will be updated on the falling

edge of the SCLK input signal. This pin will be tri-stated upon completion of

data transfer.

DS3

/E3_2 I

DS3/E3 Select Input - channel 2:

See description pin 8

Internal 50 K Ohm pull-down resistor.

VDD ****

Digital Power Supply = 5V±5% or 3.3V±5%

NC No Connection

RCLKES I

Received Clock Edge Select Input:

Hardware Mode

1. When RCLKES = “0”, then RPOS and RNEG are updated on the falling

edge of RCLK

2. When RCLKES = “1”, then RPOS and RNEG are updated on the rising

edge of RCLK

OTE

This applies to all channels.

Host Mode

Connect this pin to GND when the 71D03 is configured in the Host Mode.

Internal 50 K Ohm pull-down resistor.

RRNEG_1 O

Received Recovered Negative Data (De-Jittered) Output - channel

See description of pin 5

RRPOS_1 O

Received Recovered Positive Data (De-Jittered) Output - channel

See description of pin 4

PIN DESCRIPTION

AME

YPE

ESCRIPTION

XRT71D03

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

RRCLK_1 O

Received Recovered Output (De-jittered) Clock - channel 1:

See description of pin 3.

GND ****

Digital Ground

AVDD ****

Analog Power Supply = 5 V±5% or 3.3V±5%

AGND ****

Analog Ground

FL_1 O

FIFO Limit - channel 1:

See description pin 18

STS1_1 I

SONET STS1 Mode Select - channel 1:

See description pin 19

MCLK_1 I

Master Clock Input - channel 1:

See description pin 28.