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TEF6892H/V3,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
2003 Oct 21 25
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6892H
Table 6 Description of data byte 1
11.1.2 DATA BYTE 2; LEVEL
Table 7 Format of data byte 2
Table 8 Description of data byte 2
BIT SYMBOL DESCRIPTION
7 STIN Stereo indicator. 0 = no pilot signal detected; 1 = pilot signal detected.
6 ASIA ASI active. 0 = not active; 1 = ASI step is in progress.
5 AFUS AF update sample. 0 = LEV, USN and WAM information is taken from main frequency
(continuous mode); 1 = LEV, USN and WAM information is taken from alternative
frequency. Continuous mode during AF update and sampled mode after AF update.
Sampled mode reverts to continuous main frequency information after read.
4 POR Power-on reset. 0 = standard operation (valid I
2
C-bus register settings); 1 = Power-on
reset detected since last read cycle (I
2
C-bus register reset). After read the bit will reset
to POR = 0.
3RDAVRDS data available. This bit indicates, that RDS block data is available.
2 to 0 ID[2:0] Identification. TEF6892H device type identification; ID[2:0] = 010.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LEV7 LEV6 LEV5 LEV4 LEV3 LEV2 LEV1 LEV0
BIT SYMBOL DESCRIPTION
7 to 0 LEV[7:0] Level. 8-bit value of level voltage from tuner; see Fig.4.
handbook, halfpage
05
V
LEVEL
(V)
V
eq
(V)
LEV
[
7:0
]
255
0
5
0
1
2
3
4
1234
MHC331
Fig.4 Equivalent level voltage V
eq
(MPH and LEV detector) as a function of level voltage V
LEVEL
.
2003 Oct 21 26
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6892H
11.1.3 DATA BYTE 3; USN AND WAM
Table 9 Format of data byte 3
Table 10 Description of data byte 3
11.1.4 D
ATA BYTE 4; RDS STATUS
Table 11 Format of data byte 4
Table 12 Description of data byte 4
11.1.5 D
ATA BYTE 5; RDS LDATM
Table 13 Format of data byte 5
Table 14 Description of data byte 5
11.1.6 DATA BYTE 6; RDS LDATL
Table 15 Format of data byte 6
Table 16 Description of data byte 6
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
USN3 USN2 USN1 USN0 WAM3 WAM2 WAM1 WAM0
BIT SYMBOL DESCRIPTION
7 to 4 USN[3:0] Ultrasonic noise detector. USN content of the MPXRDS audio signal; see Fig.5.
3 to 0 WAM[3:0] Wideband AM detector. WAM content of the LEVEL voltage; see Fig.6.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SYNC DOFL RSTD LBI2 LBI1 LBI0 ELB1 ELB0
BIT SYMBOL DESCRIPTION
7 SYNC Synchronization found status. 0 = synchronization is searched. 1 = synchronization
found.
6 DOFL Data overflow flag. 0 = normal operation. 1 = data overflow is detected (no update).
5 RSTD Reset detected. 0 = normal operation. 1 = decoder reset (POR) is in progress.
4 to 2 LBI[2:0] Last block identification. See Table 25.
1 and 0 ELB[1:0] Error status last block. See Table 26.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LM15 LM14 LM13 LM12 LM11 LM10 LM9 LM8
BIT SYMBOL DESCRIPTION
7 to 0 LM[15:8] Block data of previously received RDS block, most significant byte.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LM7 LM6 LM5 LM4 LM3 LM2 LM1 LM0
BIT SYMBOL DESCRIPTION
7 to 0 LM[7:0] Block data of previously received RDS block, least significant byte.
2003 Oct 21 27
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6892H
11.1.7 DATA BYTE 7; RDS PDATM
Table 17 Format of data byte 7
Table 18 Description of data byte 7
11.1.8 DATA BYTE 8; RDS PDATL
Table 19 Format of data byte 8
Table 20 Description of data byte 8
11.1.9 DATA BYTE 9; RDS COUNT
Table 21 Format of data byte 9
Table 22 Description of data byte 9
11.1.10 D
ATA BYTE 10; RDS PBIN
Table 23 Format of data byte 10
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8
BIT SYMBOL DESCRIPTION
7 to 0 PM[15:8] Block data of previously received RDS block, most significant byte. Only relevant when
reduced data request mode is active (DAC = 10; see Table 40).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0
BIT SYMBOL DESCRIPTION
7 to 0 PM[7:0] Block data of previously received RDS block, least significant byte. Only relevant when
reduced data request mode is active (DAC = 10; see Table 40).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BBC5 BBC4 BBC3 BBC2 BBC1 BBC0 GBC5 GBC4
BIT SYMBOL DESCRIPTION
7 to 2 BBC[5:0] Bad block counter. Counter value of received invalid blocks; n=0to63.
1 and 0 GBC[5:4] Good block counter. Two most significant bits of received valid blocks counter;
n = 0 to 62. Remark: the least significant bit is not available for reading (assume
GBC0 = 0).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GBC3 GBC2 GBC1 PBI2 PBI1 PBI0 EPB1 EPB0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

TEF6892H/V3,557

Mfr. #:
Buy TEF6892H/V3,557
Manufacturer:
NXP Semiconductors
Description:
IC AUDIO TONE PROCESSOR 44PQFP
Lifecycle:
New from this manufacturer.
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