1/11August 2004
■ HIGH SPEED:
t
PD
= 5.8 ns (TYP.) at V
CC
= 3.3V
■ 5V TOLERANT INPUTS
■ INPUT VOLTAGE LEVEL:
V
IL
=0.8V, V
IH
=2V at V
CC
=3V
■ LOW POWER DISSIPATION:
I
CC
= 2 µA (MAX.) at T
A
=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 86
■ IMPROVED LATCH-UP IMMUNITY
■ POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX86 is a low voltage CMOS QUAD
EXCLUSIVE OR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVX86
LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX86MTR
TSSOP 74LVX86TTR
TSSOPSOP
Rev. 4
